TLP113 Datasheet, PDF (4/8 Pages) Toshiba Semiconductor – Isolated Line Receiver Simplex / Multiplex Data Transmission Computer.Peripheral Interface Microprocessor System Interface Digital Isolation For A / D

TLP113
Switching Characteristics (V_CC=5V, Ta=25°C)
Characteristic
Propagation delay time
(H®L)
Propagation delay time
(L®H)
Output rise-fall time
(10-90%)
Common mode transient
imunity at high output
level
Common mode transient
imunity at low output
level
Symbol
t_pHL
t_pLH
t_r, t_f
CM_H
CM_L
Test
Cir-
Test Condition
cuit
1
I_F=0®16mA
C_L=15pF, R_L=350W
1
I_F=16®0mA
C_L=15pF, R_L=350W
2
R_L=350W, C_L=15pF
I_F=0 16mA
2
I_F=0mA, V_CM=200V_p-p
V_O(min)=2V, R_L=350W
I_F=16mA, V_CM=200V_p-p
2
V_O(max)=0.8V,
R_L=350W
Min.
Typ.
Max. Unit
―
60
120
ns
―
60
120
ns
―
30
―
ns
―
200
― V / ms
―
-500
― V / ms
(Note 4) Device considered a two-terminal device: Pins 1 and 3 shorted together, and pins 4, 5 and 6 shorted
together.
(Note 5) The V_CC supply voltage to each TLP113 isolator must be bypassed by 0.1mF capacitor, this can be either a
ceramic or solid tantalum capacitor with good high frequency characteristic and should be connected as
close as possible to package V_CC and GND pins of each device.
(Note 6) Maximum electrostatic discharge voltage for any pins: 180V(C=200pF, R=0)
4
2002-09-25