TC74HC4017AP_07 Datasheet, PDF (5/9 Pages) Toshiba Semiconductor – CMOS Digital Integrated Circuit Silicon Monolithic Decade Counter/Divider

Timing Requirements (input: t_r = t_f = 6 ns)
Characteristics
Symbol
Minimum pulse width
(CK)
Minimum pulse width
(CLR)
t_{W (L)}
t_{W (H)}
t_{W (H)}
Minimum set-up time
t_s
Minimum hold time
t_h
Minimum removal time
t_rem
(CLR)
Clock frequency
f
TC74HC4017AP/AF
Test Condition
⎯
⎯
⎯
⎯
⎯
⎯
V_CC (V)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Ta = 25°C
Typ. Limit
⎯
75
⎯
15
⎯
13
⎯
75
⎯
15
⎯
13
⎯
50
⎯
10
⎯
9
⎯
75
⎯
15
⎯
13
⎯
50
⎯
10
⎯
9
⎯
5
⎯
25
⎯
29
Ta =
−40
~85°C
Limit
95
19
16
95
19
16
60
12
11
95
19
16
60
12
11
4
20
25
Unit
ns
ns
ns
ns
ns
MHz
AC Characteristics (C_L = 15 pF, V_CC = 5 V, Ta = 25°C, input: t_r = t_f = 6 ns)
Characteristics
Symbol
Test Condition
Min Typ. Max Unit
Output transition time
t_TLH
t_THL
Propagation delay time
t_pLH
(CK, CE -Q, CARRY)
t_pHL
Propagation delay time
t_pLH
(CLR-Q, CARRY)
t_pHL
Maximum clock frequency
f_max
⎯
⎯
6
12
ns
⎯
⎯
21
34
ns
⎯
⎯
19
30
ns
⎯
29
87
⎯ MHz
5
2007-10-01