TC58NS256DC Datasheet, PDF (5/33 Pages) Toshiba Semiconductor – TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 256-MBIT (32M ®8 BITS) CMOS NAND E2PROM (32M BYTE SmartMediaTM)

TC58NS256DC
Notes:
(1) CE High to Ready time depends on the pull-up resistor tied to the RY/BY pin.
(Refer to Application Note (7) toward the end of this document.)
(2) Sequential Read is terminated when tCEH is greater than or equal to 100 ns.
If the RE to CE delay is less than 30 ns, RY/BY signal stays Ready.
t_CEH ≥ 100 ns
*
*: V_IH or V_IL
CE
RE
525
526
527
A
RY/BY
Busy
A : 0~30 ns → Busy signal is not output.
PROGRAMMING AND ERASING CHARACTERISTICS
(Ta = 0°~55°C, V_CC = 3.3 V ± 0.3 V)
SYMBOL
PARAMETER
MIN
t_PROG
N
Programming Time

Number of Programming Cycles on Same

Page
t_BERASE
Block Erasing Time

P/E
Number of Program/Erase Cycles

(1) Refer to Application Note 12 toward the end of this document.
(2) Refer to Application Note 15 toward the end of this document.
TYP.
200

3

MAX
1000
10
4
2.5 x 10⁵
UNIT
µs
ms
NOTES
(1)
(2)
2000-08-27 5/33