TC58NS256DC Datasheet, PDF(22/33 Page) Toshiba Semiconductor – TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 256-MBIT (32M ®8 BITS) CMOS NAND E2PROM (32M BYTE SmartMediaTM)

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TC58NS256DC Datasheet, PDF (22/33 Pages) Toshiba Semiconductor – TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 256-MBIT (32M ®8 BITS) CMOS NAND E2PROM (32M BYTE SmartMediaTM)

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TC58NS256DC

Reset

The Reset mode stops all operations. For example, in the case of a Program or Erase operation the internally

generated voltage is discharged to 0 volts and the device enters Wait state.

The address and data registers are set as follows after a Reset:

â¢ Address Register: All 0

â¢ Data Register: All 1

â¢ Operation Mode: Wait state

The response to an FFH Reset command input during the various device operations is as follows:

When a Reset (FFH) command is input during programming

Internal VPP

RY/BY

tRST (max 10 Âµs)

Figure 8.

When a Reset (FFH) command is input during erasing

Internal erase

voltage

RY/BY

tRST (max 500 Âµs)

Figure 9.

When a Reset (FFH) command is input during a Read operation

RY/BY

tRST (max 6 Âµs)

Figure 10.

2000-08-27 22/33

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