TMP86PM29BUG Datasheet, PDF (45/204 Pages) Toshiba Semiconductor – 8 Bit Microcontroller

TMP86PM29BUG
2.3 Reset Circuit
The TMP86PM29BUG has four types of reset generation procedures: An external reset input, an address trap
reset, a watchdog timer reset and a system clock reset. Of these reset, the address trap reset, the watchdog timer and
the system clock reset are a malfunction reset. When the malfunction reset request is detected, reset occurs during
the maximum 24/fc[s] (The RESET pin outputs "L" level).
The malfunction reset circuit such as watchdog timer reset, address trap reset and system clock reset is not initial-
ized when power is turned on. Therefore, reset may occur during maximum 24/fc[s] (1.5µs at 16.0 MHz) when
power is turned on. RESET pin outputs "L" level during maximum 24/fc[s] (1.5µs at 16.0MHz).
Table 2-3 shows on-chip hardware initialization by reset action.
Table 2-3 Initializing Internal Status by Reset Action
On-chip Hardware
Initial Value
On-chip Hardware
Program counter
(PC) (FFFEH)
Stack pointer
(SP)
General-purpose registers
(W, A, B, C, D, E, H, L, IX, IY)
Not initialized
Not initialized
Prescaler and divider of timing generator
Jump status flag
(JF) Not initialized Watchdog timer
Zero flag
(ZF) Not initialized
Carry flag
(CF) Not initialized
Half carry flag
Sign flag
(HF)
(SF)
Not initialized
Not initialized
Output latches of I/O ports
Overflow flag
(VF) Not initialized
Interrupt master enable flag
(IMF)
0
Interrupt individual enable flags (EF)
0
Control registers
Interrupt latches
(IL)
0
LCD data buffer
RAM
Initial Value
0
Enable
Refer to I/O port circuitry
Refer to each of control
register
Not initialized
Not initialized
2.3.1 External Reset Input
The RESET pin contains a Schmitt trigger (Hysteresis) with an internal pull-up resistor.
When the RESET pin is held at “L” level for at least 3 machine cycles (12/fc [s]) with the power supply volt-
age within the operating voltage range and oscillation stable, a reset is applied and the internal state is initial-
ized.
When the RESET pin input goes high, the reset operation is released and the program execution starts at the
vector address stored at addresses FFFEH to FFFFH.
VDD
RESET
Internal reset
Malfunction
reset output
circuit
Figure 2-15 Reset Circuit
Page 31
Watchdog timer reset
Address trap reset
System clock reset