TMP86PM29BUG Datasheet, PDF (136/204 Pages) Toshiba Semiconductor – 8 Bit Microcontroller

11. Asynchronous Serial interface (UART )
11.2 Control
TMP86PM29BUG
11.2 Control
UART is controlled by the UART Control Registers (UARTCR1, UARTCR2). The operating status can be moni-
tored using the UART status register (UARTSR).
UART Control Register1
UARTCR1
7
6
5
4
3
(0025H)
TXE RXE STBT EVEN PE
2
1
0
BRG
(Initial value: 0000 0000)
TXE
Transfer operation
RXE Receive operation
STBT Transmit stop bit length
EVEN Even-numbered parity
PE
Parity addition
BRG Transmit clock select
0: Disable
1: Enable
0: Disable
1: Enable
0: 1 bit
1: 2 bits
0: Odd-numbered parity
1: Even-numbered parity
0: No parity
1: Parity
000: fc/13 [Hz]
001: fc/26
010: fc/52
011: fc/104
100: fc/208
101: fc/416
110: TC5 ( Input INTTC5)
111: fc/96
Write
only
Note 1: When operations are disabled by setting TXE and RXE bit to “0”, the setting becomes valid when data transmit or receive
complete. When the transmit data is stored in the transmit data buffer, the data are not transmitted. Even if data transmit is
enabled, until new data are written to the transmit data buffer, the current data are not transmitted.
Note 2: The transmit clock and the parity are common to transmit and receive.
Note 3: UARTCR1<RXE> and UARTCR1<TXE> should be set to “0” before UARTCR1<BRG> is changed.
UART Control Register2
UARTCR2
7
6
5
4
3
2
1
0
(0026H)
RXDNC
STOPBR (Initial value: **** *000)
Selection of RXD input noise
RXDNC
rejection time
STOPBR Receive stop bit length
00: No noise rejection (Hysteresis input)
01: Rejects pulses shorter than 31/fc [s] as noise
10: Rejects pulses shorter than 63/fc [s] as noise
11: Rejects pulses shorter than 127/fc [s] as noise
0: 1 bit
1: 2 bits
Write
only
Note: When UARTCR2<RXDNC> = “01”, pulses longer than 96/fc [s] are always regarded as signals; when UARTCR2<RXDNC>
= “10”, longer than 192/fc [s]; and when UARTCR2<RXDNC> = “11”, longer than 384/fc [s].
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