TMP88CH41UG Datasheet, PDF (41/186 Pages) Toshiba Semiconductor – 8 Bit Microcontroller

TMP88CH41UG
Main task
Bank m
Interrupt
acceptance
Interrupt
service task
Bank m
Bank n
Switch to bank n by
LD, RBS and n instruction
Switch to bank n
automatically
Main task
Interrupt
acceptance
Interrupt
service task
Saving
registers
Bank m
Interrupt return
Restore to bank m
automatically by
[RETI]/[RETN]
Restoring
registers
Interrupt return
(a) Saving/restoring by register bank changeover
(b) Saving/restoring general-purpose registers using
PUSH/POP data transfer instruction
Figure 3-4 Saving/Restoring General-purpose Registers under Interrupt Processing
3.3.3 Interrupt return
Interrupt return instructions [RETI]/[RETN] perform as follows.
[RETI] Maskable Interrupt Return
1. The contents of the program counter and the
program status word are restored from the stack.
2. The stack pointer is incremented 5 times.
3. The interrupt master enable flag is set to "1".
4. The interrupt nesting counter is decremented,
and the interrupt nesting flag is changed.
[RETN] Non-maskable Interrupt Return
1. The contents of the program counter and the
program status word are restored from the stack.
2. The stack pointer is incremented 5 times.
3. The interrupt master enable flag is set to "1" only
when a non-maskable interrupt is accepted in
interrupt enable status. However, the interrupt
master enable flag remains at "0" when so clear
by an interrupt service program.
4. The interrupt nesting counter is decremented,
and the interrupt nesting flag is changed.
Interrupt requests are sampled during the final cycle of the instruction being executed. Thus, the next inter-
rupt can be accepted immediately after the interrupt return instruction is executed.
Note: When the interrupt processing time is longer than the interrupt request generation time, the interrupt service
task is performed but not the main task.
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