TMP88CH41UG Datasheet, PDF (103/186 Pages) Toshiba Semiconductor – 8 Bit Microcontroller

TMP88CH41UG
11.3 Function
TimerCounter 4 has four types of operating modes: timer, event counter, programmable divider output (PDO), and
pulse width modulation (PWM) output modes.
11.3.1 Timer Mode
In the timer mode, the up-counter counts up using the internal clock. When a match between the up-counter
and the TC4DR value is detected, an INTTC4 interrupt is generated and the up-counter is cleared. After being
cleared, the up-counter restarts counting.
Table 11-1 Internal Source Clock for TimerCounter 4 (Example: fc = 20 MHz)
TC4CK
000
001
010
011
NORMAL, IDLE Mode
DV1CK = 0
DV1CK = 1
Resolution
[μs]
Maximum Time Setting
[ms]
Resolution
[μs]
Maximum Time Setting
[ms]
102.4
26.11
204.8
52.22
6.4
1.63
12.8
3.28
1.6
0.41
3.2
0.82
0.4
0.10
0.8
0.20
11.3.2 Event Counter Mode
In the event counter mode, the up-counter counts up at the rising edge of the input pulse to the TC4 pin.
When a match between the up-counter and the TC4DR value is detected, an INTTC4 interrupt is generated
and the up-counter is cleared. After being cleared, the up-counter restarts counting at rising edge of the TC4
pin. Since a match is detected at the falling edge of the input pulse to the TC4 pin, the INTTC4 interrupt
request is generated at the falling edge immediately after the up-counter reaches the value set in TC4DR.
The minimum pulse width applied to the TC4 pin are shown in Table 11-2. The pulse width larger than two
machine cycles is required for high- and low-going pulses.
Note:The event counter mode can used in the NORMAL and IDLE modes only.
Table 11-2 External Source Clock for TimerCounter 4
High-going
Low-going
Minimum Pulse Width
NORMAL, IDLE mode
2³/fc
2³/fc
11.3.3 Programmable Divider Output (PDO) Mode
The programmable divider output (PDO) mode is used to generated a pulse with a 50% duty cycle by count-
ing with the internal clock.
When a match between the up-counter and the TC4DR value is detected, the logic level output from the
PDO4 pin is switched to the opposite state and INTTC4 interrupt request is generated. The up-counter is
cleared at this time and then counting is continued. When a match between the up-counter and the TC4DR
value is detected, the logic level output from the PDO4 pin is switched to the opposite state again and INTTC4
interrupt request is generated. The up-counter is cleared at this time, and then counting and PDO are continued.
When the timer is stopped, the PDO4 pin is high. Therefore, if the timer is stopped when the PDO4 pin is
low, the duty pulse may be shorter than the programmed value.
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