TC9318AFAG Datasheet, PDF (40/56 Pages) Toshiba Semiconductor – Single Chip DTS Microcontroller (DTS-21)

TC9318AFAG/AFBG
Key Return Timing Output Port (T0~T5)
T0~T5 are exclusive output port of 6 bits with N-channel load resostors. Normally, T0~T5 is used as output of
key return timing Signal for Key matrix.
This output port is made access by OUT2 instruction designated the operand part [CN = 8 or 9] (φL28 or
φL29).
Note 36: During the clock stop mode (excusing CKSTP instruction), T0~T3 and OT0, OT1 output is fixed at “L” level
automatically, but the content of port is held on the previous data.
Buzzer Output (BUZR)
The buzzer output is used for such purposes as audible alarms or to issue confirmation beeps for key-presses
or tuning scan mode. The buzzer frequency can be set as desired. 50% duty waveform is output.
1. BUZR Data Port
The BUZR output can also be used as the P3-1 I/O port. To switch the P3-1 output to BUZR output, set
“1” to BUZR ON bit.
It is necessary to set of the BUZR data before setting the BUZRON bit to “1”.
Setting the data to BUZR data port (φL1C), the BUZR data is transferred to the BUZR data Latch, and
then changed BUZR frequency.
The BUZR output has a frequency of 75 kHz divided by 2 × n (n = B0~B7). The B0~B7 setting range and
frequency range is 2 ^<= n ^<= 255. This can be expressed as a formula as follows.
75 kHz
2×2
= 18.75 kHz
<= _ƒBUZR <=
75 kHz _{= 147 Ηz}
2 × 255
Set B0~B7 to 1 or 0 to use the pin for OT1 output. The output states are as follows.
B7 B6 B5 B4 B3 B2 B1 B0
00000000
00000001
OT1 Output
Low level output
High level output
To set the above data, use the OUT1 instruction with the operand [CN = BH~EH].
Note 37: After a system reset, the BUZR data port is reset to “0”.
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2006-07-27