TC9318AFAG Datasheet, PDF (1/56 Pages) Toshiba Semiconductor – Single Chip DTS Microcontroller (DTS-21)

TC9318AFAG/AFBG
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC9318AFAG,TC9318AFBG
Single Chip DTS Microcontroller (DTS-21)
The TC9318AFAG and TC9318AFBG are a 4 bit CMOS
microcontroller for signal chip digital tuning systems. It is
capable of functioning at a low voltage of 3 V and features a
built-in prescaler of operating 230 MHz, PLL and LCD drivers.
The CPU has 4 bit parallel addition and subtraction
instructions (e.g., AI, SI), logic operation instructions (e.g., OR,
AN), composite judging and compare instructions (e.g., TM, SL),
and time-base functions.
The package is an pin 64, 0.5/0.65-mm-pitch quad flat pack
package. In addition to various input/output ports and a
dedicated key-input port, which are controlled by powerful
input/output instructions (IN 1, 2, OUT 1, 2), there are many
dedicated LCD pins, a buzzer port, a 6 bit A/D converter, an IF
counter, and other pins.
Low-voltage and low-current consumption make this
microcontroller suitable for portable DTS equipment.
TC9318AFAG
TC9318AFBG
Features
• 4 bit microcontroller for digital tuning systems.
• Operating voltage VDD = 1.8~3.6 V, with low current
consumption because of CMOS circuitry (with only CPU
operating, when VDD = 3 V, IDD = 80 µA max)
• Built-in prescaler (1/2 fixed divider +2 modulus prescaler:
fmax ≥ 230 MHz)
Weight
P-LQFP64-1010-0.50E: 0.32 g (typ.)
P-LQFP64-1212-0.65A: 0.45 g (typ.)
• Features built-in 1/3-duty, 1/2-bias LCD drivers and a built-in 3 V booster circuit for the display.
• Data memory (RAM) and ports are easily backed up.
• Program memory (ROM): 16 bit × 4096 steps
• Data memory (RAM): 4 bit × 256 words
• 60-instruction set (all one-word instructions)
• Instruction execution time: 40 µs (with 75 kHz crystal) (MVGS, DAL instructions: 80 µs)
• Many addition and subtraction instructions (12 types addition, 12 types subtraction)
• Powerful composite judging instructions (TMTR, TMFR, TMT, TMF, TMTN, TMFN)
• Data can be transmitted between addresses on the same row. (MVSR instruction)
• Register indirect transfer available (MVGD, MVGS instruction).
• 16 powerful general registers (located in RAM)
• Stack levels: 2
• JUMP or CAL instruction can be used anywhere in the 4096 steps of program memory (ROM) as there are no
pages or fields.
• 16 bit of any address in the 1024 steps in program memory (ROM) can be referenced (DAL instruction).
• Features independent frequency input pins (FMIN and AMIN) and two (DO1 and DO2) phase comparison
outputs for FM/VHF and AM.
• Seven reference frequencies can be selected by program.
• Powerful input/output instructions (IN 1, 2, OUT 1, 2)
• Dedicated input ports (K0~K3) for key input. 26 LCD drive pins (69 segments maximum) available.
• 17 I/O ports: 10 with input/output programmable in 1 bit units, and 7 output-only port. The 2 IFIN, and DO1
pins can be switched by instruction to IN (input-only) or OT (output-only).
• Three back-up modes available by instruction: Only CPU operation, crystal oscillation only, clock stop.
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2006-07-27