TLP2200_07 Datasheet, PDF (4/7 Pages) Toshiba Semiconductor – High Speed Line Receiver

TLP2200
Switching Characteristics
(unless otherwise specified, Ta = 0~85°C,V_CC = 4.5~20V,I_F(ON) = 1.6~5mA,I_F(OFF) = 0~0.1mA)
Characteristic
Symbol
Propagation delay time to
logic high output level
(Note 5)
Propagation delay time to
logic low output level
(Note 5)
Output rise time (10−90%)
Output fall time (90−10%)
Output enable time to
logic high
Output enable time to
logic low
Output disable time from
logic high
Output disable time from
logic low
Common mode transient
immunity at logic high
output
(Note 6)
Common mode transient
immunity at logic low
output
(Note 6)
t_pLH
t_pHL
t_r
t_f
t_pZH
t_pZL
t_pHZ
t_pLZ
CM_H
CM_L
Test
Cir−
Test Condition
cuit
Without peaking capacitor
C₁
With peaking capacitor C₁
Without peaking capacitor
1
C₁
With peaking capacitor C₁
―
―
Min. Typ. Max. Unit
― 235 ―
ns
―
―
400
― 250 ―
ns
―
―
400
―
35
―
ns
―
20
―
ns
―
―
―
ns
―
―
―
―
ns
2
―
―
―
―
ns
―
―
―
―
ns
I_F = 1.6mA, V_CM = 50V,
Ta = 25°C
3
I_F = 0mA, V_CM = 50V,
Ta = 25°C
−1000 ―
― V / μs
1000 ―
― V / μs
(*) All typ. values are at Ta = 25°C, V_CC = 5V, I_F(ON) = 3mA unless otherwise specified.
(Note 4) Duration of output short circuit time should not exceed 10ms.
(Note 5) The t_pLH propagation delay is measured from the 50% point on the leading edge of the input pulse to the
1.3V point on the leading edge of the output pulse.
The t_pHL propagation delay is measured from the 50% point on the trailing edge of the input pulse to the
1.3V point on the trailing edge of the output pulse.
(Note 6) CM_L is the maximum rate of rise of the common mode voltage that can be sustained with the output
voltage in the logic low state (V_O ≤ 0.8V).
CM_H is the maximum rate of fall of the common mode voltage that can be sustained with the output
voltage in the logic high state (V_O ≤ 2.0V).
4
2007-10-01