TC55W800XB7 Datasheet, PDF (4/12 Pages) Toshiba Semiconductor – 524,288-WORD BY 16-BIT FULL CMOS STATIC RAM

TC55W800XB7,8
DC CHARACTERISTICS (Ta = −40° to 85°C, V_DD = 2.3 to 3.3 V)
SYMBOL
I_IL
I_OH
I_OL
I_LO
PARAMETER
Input Leakage
Current
Output High Current
Output Low Current
Output Leakage
Current
TEST CONDITION
V_IN = 0 V~V_DD
V_OH = V_DD − 0.5 V
V_OL = 0.4 V
CE1 = V_IH or CE2 = V_IL or LB and UB = V_IH
or R/W = V_IL or OE = V_IH, V_OUT = 0 V~V_DD
MIN TYP MAX UNIT
  ±1.0 µA
−0.5 
2.1 
 mA
 mA
  ±1.0 µA
l_DDO1
l_DDO2
Operating Current
CE1 = V_IL and CE2 = V_IH and
LB and UB = V_IL and R/W = V_IH and
I_OUT = 0 mA and Other Input = V_IH/V_IL
CE1 = 0.2 V and CE2 = V_DD − 0.2 V and
LB and UB = 0.2 V,
R/W = V_DD − 0.2 V and I_OUT = 0 mA,
Other Input = V_DD − 0.2 V/0.2 V
min
  50
t_cycle
mA
1 µs   10
min
  45
t_cycle
mA
1 µs   5
I_DDS1
I_DDS2
(Note)
Standby Current
CE1 = V_IH or CE2 = V_IL or LB and UB = V_IH
  2 mA
CE1 = V_DD − 0.2 V
or CE2 = 0.2 V
or LB and UB =
V_DD − 0.2 V,
V_DD = 1.5 V~3.3 V
V_DD =
Ta = 25°C
 1
3.0 V ± 10% _{Ta = −40~85°C   10}
Ta = 25°C
 0.05 0.5 µA
V_DD = 3.0 V Ta = −40~40°C  
1
Ta = −40~85°C   5
Note ŋ In standby mode with CE1 ≥ V_DD − 0.2 V, these limits are assured for the condition CE2 ≥ V_DD − 0.2 V or CE2 ≤ 0.2 V.
ŋ In standby mode with LB and UB ≥ V_DD − 0.2 V, these limits are assured for the condition CE1 ≥ V_DD − 0.2 V or CE1
≤ 0.2 V and CE2 ≥ V_DD − 0.2 V or CE2 ≤ 0.2 V.
CAPACITANCE (Ta = 25°C, f = 1 MHz)
SYMBOL
PARAMETER
TEST CONDITION
C_IN
Input Capacitance
V_IN = GND
C_OUT
Output Capacitance
V_OUT = GND
Note: This parameter is periodically sampled and is not 100% tested.
MAX
10
10
UNIT
pF
pF
2001-10-03 4/12