TC55V8512FTI-12 Datasheet, PDF (4/10 Pages) Toshiba Semiconductor – TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

TC55V8512JI/FTI-12,-15
AC CHARACTERISTICS (Ta = −40° to 85°C ^{(See Note 1)}, V_DD = 3.3 V ± 0.3 V)
READ CYCLE
SYMBOL
PARAMETER
t_RC
t_ACC
t_CO
t_OE
t_OH
t_COE
t_OEE
t_COD
t_ODO
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Output Data Hold Time from Address Change
Output Enable Time from Chip Enable
Output Enable Time from Output Enable
Output Disable Time from Chip Enable
Output Disable Time from Output Enable
TC55V8512JI/FTI
-12
-15
MIN
MAX
MIN
MAX
12

15


12

15

12

15

6

8
3

4

3

4

1

1


7

8

7

8
UNIT
ns
WRITE CYCLE
SYMBOL
PARAMETER
t_WC
t_WP
t_CW
t_AW
t_AS
t_WR
t_DS
t_DH
t_OEW
t_ODW
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Address Valid to End of Write
Address Setup Time
Write Recovery Time
Data Setup Time
Data Hold Time
Output Enable Time from Write Enable
Output Disable Time from Write Enable
TC55V8512JI/FTI
-12
-15
MIN
MAX
MIN
MAX
12

15

8

9

10

12

10

12

0

0

0

0

7

8

0

0

1

1


7

8
UNIT
ns
AC TEST CONDITIONS
PARAMETER
Input Pulse Level
Input Pulse Rise and Fall Time
Input Timing Measurement
Reference Level
Output Timing Measurement
Reference Level
Output Load
TEST CONDITION
3.0 V/ 0.0 V
2 ns
1.5 V
1.5 V
Fig.1
Fig.1
I/O pin ^Z0 ^{= 50 Ω}
3.3 V
I/O pin
1200 Ω
C_L = 30 pF
R_L = 50 Ω
C_L = 5 pF
870 Ω
V_L = 1.5 V
(For t_COE, t_OEE, t_COD,
t_ODO, t_OEW and t_ODW)
2001-12-19 4/10