HN7G02FU_07 Datasheet, PDF (4/6 Pages) Toshiba Semiconductor – Power Management Switch Application, Inverter Circuit

Q2 (MOS-FET)
(a) Switching time test circuit
2.5 V
IN
0
10 μS
V_IN
I_D
V_DD = 3 V
OUT _D.U. <= _1%
V_IN: t_r, t_f < 5 ns
(Z_out = 50 Ω)
Common source
Ta = 25°C
V_DD
(b) V_IN
V_GS
(c) V_OUT
V_DS
HN7G02FU
2.5 V
90%
0
V_DD
V_{DS (ON)}
10%
90%
10%
t_r
t_f
t_on
t_off
60
50 _2.5 2.2
I_D – V_DS
Common source
Ta = 25°C
40
2.0
30
1.8
20
1.6
10
VGS = 1.4 V
1.2
0
0
2
4
6
8
10
12
Drain-source voltage V_DS (V)
1.2
1.0 _2.5
1.2
0.8
0.6
I_D – V_DS (低電圧領域)
Common source
1.1
Ta = 25°C
1.05
0.4
VGS = 1.0 V
0.2
0.95
0.9
0.8
0
0
0.1
0.2
0.3
0.4
0.5
0.6
Drain-source voltage V_DS (V)
I_DR – V_DS
50
30
Common source
VGS = 0
10
Ta = 25°C
5
3
D
1
G
IDR
0.5
0.3
S
0.1
0.05
0.03
0.01
0 −0.2 −0.4 −0.6 −0.8 −1.0 −1.2 −1.4 −1.6 −1.8
Drain-source voltage V_DS (V)
50
30
10
5 ^{Ta = 100°C}
3
I_D – V_GS
Common source
VDS = 3 V
1
0.5
0.3
25
0.1
−25
0.05
0.03
0.01
0
1
2
3
4
5
Gate-source voltage V_GS (V)
4
2007-11-01