TMPR3911 Datasheet, PDF (354/462 Pages) Toshiba Semiconductor – 32-Bit TX System RISC TX39 Family

17.4.4 Video Control 4 Register
Chapter 17 Video Module
OFFSET = $034:
write-only
Bit
31-24
23-20
19-4
3-0
Label
DFVAL[7:0]
FRAMEMASKVAL[3:0]
VIDBASELO[19:0]
Reserved
RESET
X
X
X
Read/Write
W
W
W
DFVAL[7:0]:
write-only
These bits define the rate at which the DF signal will toggle if the DFMODE bit is set. The DF
counter counts on each LOAD pulse, thus the DF Rate is given by the following equation:
DF Rate = ^LineRate
DFVAL[7 :0]+ 1
VIDBASELO[19:4]:
write-only
These bits provide the start address for the lower address counter. If a non-split LCD is used,
these bits must be set to “1” plus the last address of the video buffer.
FRAMEMASKVAL[3:0]:
These bits determine the number of lines for which the VIDDONE signal will not assert
following the assertion of the FRAME signal. If these bits are set to $0 then the VIDDONE signal
will assert after every line completes shifting. Setting these bits to $1 will cause the VIDDONE
signal to not assert after the line that immediately follows the assertion of the FRAME signal.
Increases in these bits will cause subsequent lines to not assert the VIDDONE signal. Use of these
bits allows the VIDDONE synchronization pulses to be generated away torn the periods after the
video FRAM and DF transitions occur.
17-22