TK40E10N1 Datasheet, PDF (3/9 Pages) Toshiba Semiconductor – Switching Voltage Regulators

TK40E10N1
6. Electrical Characteristics
6.1. Static Characteristics (T_a = 25 unless otherwise specified)
Characteristics
Symbol
Test Condition
Min Typ. Max Unit
Gate leakage current
I_GSS
V_GS = ±20 V, V_DS = 0 V


±0.1
µA
Drain cut-off current
I_DSS
V_DS = 100 V, V_GS = 0 V


10
Drain-source breakdown voltage
Drain-source breakdown voltage
(Note 4)
V_(BR)DSS I_D = 10 mA, V_GS = 0 V
V_(BR)DSX I_D = 10 mA, V_GS = -20 V
100


V
65


Gate threshold voltage
V_th
V_DS = 10 V, I_D = 0.5 mA
2.0

4.0
Drain-source on-resistance
R_DS(ON) V_GS = 10 V, I_D = 20 A

6.8
8.2
mΩ
Note 4: If a reverse bias is applied between gate and source, this device enters V_(BR)DSX mode. Note that the drain-
source breakdown voltage is lowered in this mode.
6.2. Dynamic Characteristics (T_a = 25 unless otherwise specified)
Characteristics
Input capacitance
Reverse transfer capacitance
Output capacitance
Gate resistance
Switching time (rise time)
Switching time (turn-on time)
Switching time (fall time)
Switching time (turn-off time)
Symbol
Test Condition
C_iss
C_rss
C_oss
r_g
t_r
t_on
t_f
t_off
V_DS = 50 V, V_GS = 0 V, f = 1 MHz

See Figure 6.2.1
Min Typ. Max Unit
 3000 
pF

29


520


2.8

Ω

14

ns

35


21


57

Fig. 6.2.1 Switching Time Test Circuit
6.3. Gate Charge Characteristics (T_a = 25 unless otherwise specified)
Characteristics
Total gate charge (gate-source plus
gate-drain)
Gate-source charge 1
Gate-drain charge
Gate switch charge
Symbol
Test Condition
Q_g
V_DD ≈ 80 V, V_GS = 10 V, I_D = 40 A
Q_gs1
Q_gd
Q_SW
Min Typ. Max Unit

49

nC

18


14


21

3
2012-02-01
Rev.2.0