TC9462F_01 Datasheet, PDF (3/17 Pages) Toshiba Semiconductor – Digital Servo Single Chip Processor

Pin Function
Pin No.
1
Symbol
TEST0
2
HSO
3
UHSO
I/O
Functional Description
I Test mode terminal. Normally, keep at open.
Playback speed mode flag output terminal.
O
UHSO
H
H
L
O
L
HSO
H
L
H
L
Playback Speed
Normal
2 times
4 times
¾
TC9462F
Remarks
With pull-up resistor.
¾
Subcode Q data emphasis flag output terminal.
4
EMPH
O Emphasis ON at “H” level and OFF at “L” level.
¾
The output polarity can invert by command.
Channel clock output terminal. (44.1 kHz)
5
LRCK
O L-ch at “L” level and R-ch at “H” level. The output polarity can
¾
invert by command.
6
V_SS
¾ Digital GND terminal.
¾
7
BCK
O Bit clock output terminal. (1.4112 MHz)
¾
8
AOUT
O Audio data output terminal.
¾
9
DOUT
O Digital data output terminal.
¾
10
MBOV
O
Buffer memory over signal output terminal.
Over at “H” level.
¾
Correction flag output terminal.
11
IPF
O At “H” level, AOUT output is made to correction impossibility
¾
by C₂ correction processing.
12
SBOK
O
Subcode Q data CRCC check adjusting result output
terminal. The adjusting result is OK at “H” level.
¾
13
CLCK
I/O
Subcode P~W data readout clock input/output terminal.
This terminal can select by command bit.
Schmitt input
14
V_DD
¾ Digital power supply voltage terminal.
¾
15
V_SS
¾ Digital GND terminal.
¾
16
DATA
O Subcode P~W data output terminal.
¾
17
SFSY
O Play-back frame sync signal output terminal.
¾
18
SBSY
O Subcode block sync signal output terminal.
¾
19
SPCK
O Processor status signal readout clock output terminal.
¾
20
SPDA
O Processor status signal output terminal.
¾
21
COFS
O
Correction frame clock output terminal.
(7.35 kHz)
¾
Internal signal (DSP internal flag and PLL clock) output
22
MONIT
O terminal. Selected by command.
¾
This terminal output the text data with serial by command.
23
V_DD
¾ Digital power supply voltage terminal.
¾
Test input/output terminal. Normally, keep at “L” level.
24
TESIO0
I The terminal that inputted the clock for read of text data by
¾
command.
25
P2V_REF
¾ PLL double reference voltage supply terminal.
¾
26
HSSW
O
This terminal is used to output PV_REF or HiZ by command.
2-state output.
(PV_REF, HiZ)
27
ZDET
O 1 bit DA converter zero detect flag output terminal.
¾
28
PDO
O
Phase difference signal output terminal of EFM signal and
PLCK signal.
3-state output.
(P2V_REF, PV_REF, V_SS)
3
2001-11-05