TC9462F_01 Datasheet, PDF (11/17 Pages) Toshiba Semiconductor – Digital Servo Single Chip Processor

4. DATA, CLCK Input/Output Timing
(1) CLCK input mode
Characteristics
Symbol
Test
Circuit
Test Condition
Clock pulse width
“H” Level
“L” Level
t_HW
¾
t_LW
¾
Input set-up time
Transfer time (1)
Transfer time (2)
“L” Level
“H” Level
“L” Level
t_Su
t_pHL1
t_pLH2
t_pHL2
¾
CLCK input mode
¾
¾
¾
SFSY/COFS
CLCK
t_pHL1
t_SU
t_pHL2
t_pLH2
t_HW
t_LW
TC9462F
Min Typ. Max Unit
200
¾
¾
200 ¾
¾
200 ¾
¾
ns
¾
¾
5
¾
¾
20
¾
¾
20
DATA
SUBP
SUBQ
(2) CLCK output mode (tHW, tLW, tpLH3; 2 times speed = 1/2, 4 times speed = 1/4)
Characteristics
Symbol
Test
Circuit
Test Condition
Min Typ. Max Unit
Clock pulse width
“H” Level
“L” Level
t_HW
¾
t_LW
¾
¾
¾ 1000
¾
¾ 1000
Transfer time (1)
Transfer time (2)
“L” Level
“H” Level
“L” Level
t_pHL1
t_pLH2
t_pHL2
¾
CLCK output mode
¾
¾
¾
¾
5
ns
¾
¾
20
¾
¾
20
Transfer time (3)
“H” Level
t_pLH3
¾
¾
¾ 900
SFSY/COFS
t_pHL1
t_pLH3
t_pHL2
t_pLH2
t_HW
t_LW
CLCK
DATA
SUBP
SUBQ
11
2001-11-05