TMP92C820FG Datasheet, PDF (289/382 Pages) Toshiba Semiconductor – Original CMOS 16-Bit Microcontroller

TMP92C820
3.16.1 Control Registers
Figure 3.16.1 shows the SDRAMC control registers. Setting these registers controls the
0H
operation of SDRAMC.
SDACR
(0250H)
7
Bit symbol
SDINI
Read/Write
R/W
After reset
0
Function
Auto
initialize
0: Disable
1: Enable
SDRAM Access Control Register
6
5
4
3
SDBUS1 SDBUS0
R/W
0
0
Selecting structure of data
bus
00: 16 bits × 1
01: 16 bits × 2
10: 32 bits × 1
2
1
0
SMUXW1 SMUXW0 SMAC
R/W
0
0
Selecting address
multiplex type
00: Type A
01: Type B
10: Type C
11: Reserved
R/W
0
SDRAM
controller
0: Disable
1: Enable
SDRAM Refresh Control Register
7
6
5
4
3
2
SDRCR
(0251H)
Bit symbol
Read/Write
SFRC
R/W
SRS2
SRS1
R/W
SRS0
SASFRC
R/W
After reset
0
0
0
0
0
Function
Self refresh Refresh interval
0: Disable 000: 78 states
1: Enable _{001: 97 states}
010: 124 states
100: 195 states
101: 210 states
110: 249 states
Auto self
refresh
0: Disable
1: Enable
011: 156 states 111: 312 states
1
0
SRC
R/W
0
Interval
refresh
0: Disable
1: Enable
Figure 3.16.1 SDRAMC Control Registers
92C820-287
2007-02-16