TMP92C820FG Datasheet, PDF (103/382 Pages) Toshiba Semiconductor – Original CMOS 16-Bit Microcontroller

TMP92C820
(2) Connection memory specification
Setting the BnOM1 to 0 bit of the control register (BnCSH) specifies the memory
type to be connected with the block address areas. The interface signal is output
according to the set memory as follows
BnOM1, BnOM0 Bit (BnCSH register)
BnOM1
0
0
1
1
BnOM0
0
1
0
1
Function
SRAM/ROM (Default)
(Reserved)
(Reserved)
SDRAM
SDRAM is set only in block address are 1.
(3) Data bus width specification
The data bus width is set for every block address area. The bus size is set by the
BnBUS1 and BnBUS0 bits of the control register (BnCSH) as follows.
BnBUS Bit (BnCSH register)
BnBUS1 BnBUS0
Function
0
0
0
1
1
0
1
1
8-bit bus mode (Default)
16-bit bus mode
32-bit bus mode
(Reserved)
This way of changing the data bus size depending on the address being accessed is
called “dynamic bus sizing”. The part where the data is output to is depended on the
data size, the bus width and the start address.
Note: Since there is a possibility of abnormal writing/reading of the data if two memories
with different bus width are put in consecutive address, do not execute a access to
both memories with one command.
92C820-101
2007-02-16