TH50VSF2582 Datasheet, PDF (27/50 Pages) Toshiba Semiconductor – SRAM AND FLASH MEMORY MIXED MULTI-CHIP PACKAGE

COMMON FLASH MEMORY INTERFACE (CFI)
TH50VSF2582/2583AASB
The TH50VSF2520/2583AASB conforms to the CFI specifications. To read information from the device, input
the Query command followed by the address. In Word Mode DQ8~DQ15 all output 0s. To exit this mode, input
the Reset command.
CFI CODE TABLE
ADDRESS A6~A0
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
DATA DQ15~DQ0
0051H
0052H
0059H
0002H
0000H
0040H
0000H
0000H
0000H
0000H
0000H
0027H
0036H
0000H
0000H
0004H
0000H
000AH
0000H
0005H
0000H
0004H
0000H
0016H
0002H
0000H
0000H
0000H
DESCRIPTION
ASCII string “QRY”
Primary OEM command set
2: AMD/FJ standard type
Address for primary extended table
Alternate OEM command set
0: none exists
Address for alternate OEM extended table
V_DD (min) (Write/Erase)
DQ7~DQ4: 1 V
DQ3~DQ0: 100 mV
V_DD (max) (Write/Erase)
DQ7~DQ4: 1 V
DQ3~DQ0: 100 mV
V_PP (min) voltage
V_PP (max) voltage
Typical time-out per single byte/word write (2^N µs)
Typical time-out for minimum size buffer write (2^N µs)
Typical time-out per individual block erase (2^N ms)
Typical time-out for full chip erase (2^N ms)
Maximum time-out for byte/word write (2^N times typical)
Maximum time-out for buffer write (2^N times typical)
Maximum time-out per individual block erase (2^N times typical)
Maximum time-out for full chip erase (2^N times typical)
Device Size (2^N byte)
Flash device interface description
2: ×8/×16
Maximum number of bytes in multi-byte write (2^N)
2001-10-25 27/50