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TH50VSF2582 Datasheet, PDF (15/50 Pages) Toshiba Semiconductor – SRAM AND FLASH MEMORY MIXED MULTI-CHIP PACKAGE
TH50VSF2582/2583AASB
DC CHARACTERISTICS (Ta = -40°~85°C, VCCs/VCCf = 2.7 V~3.6 V)
SYMBOL
PARAMETER
CONDITIONS
MIN TYP. MAX UNIT
IIL
Input Leakage Current
VIN = 0 V~VCC
  ±1 µA
ISOH
SRAM Output High Current
VOH = VCCs − 0.5 V
−0.5   mA
ISOL
SRAM Output Low Current
VOL = 0.4 V
2.1   mA
IFOH1 Flash Output High Current (TTL) VOH = 2.4 V
−0.4   mA
IFOH2
Flash Output High Current
(CMOS)
VOH = VCCf × 0.85
VOH = VCCf − 0.4 V
−2.5 
−100 
 mA
 µA
IFOL
Flash Output Low Current
VOL = 0.4 V
4   mA
ILO
ICCO1
ICCO2
Output Leakage Current
Flash Average Read Current
Flash Average Program/
Erase Current
VOUT = 0 V~VCC, OE = VIH
CEF = VIL, OE = VIH, IOUT = 0 mA,
tcycle = tRC(min)
CEF = VIL, OE = VIH, IOUT = 0 mA
  ±1 µA
  30 mA
  15 mA
ICCO3
ICCO4
SRAM Average Operating
Current
CE1S = VIL, CE2S = VIH,
OE = VIH, IOUT = 0 mA
tcycle = tRC
  50
mA
tcycle = 1 MHz   12
CE1S = 0.2 V, OE = VCCs − 0.2 V, tcycle = tRC
  45
mA
CE2S = VCCs − 0.2 V, IOUT = 0 mA tcycle = 1 MHz

5
ICCO5
Flash Average
Read-while-Programming
Current
VIN = VIH/VIL, IOUT = 0 mA, tcycle = tRC(min)
  45 mA
ICCO6
ICCO7
Flash Average
Read-while-Erasing Current
Flash Average Program-while-
Erase-Suspended Current
VIN = VIH/VIL, IOUT = 0 mA, tcycle = tRC(min)
VIN = VIH/VIL, IOUT = 0 mA
  45 mA
  15 mA
ICCS1
ICCS2
Flash Standby Current
Flash Standby Current
(Automatic Sleep Mode(1))
CEF = RESET = VCCf or RESET = VSS
VIH = VCCf or VIL = VSS
  10 µA
  10 µA
ICCS3
CE1S = VIH or CE2S = VIL
Ta = 25°C
  2 mA
 0.01 0.5
Ta =
VCCs = 3.0 V −20°~40°C
 1
ICCS4
SRAM Standby Current
VCoEr1SCE2=SV=CC0s.2−V0(.22)
VCCs
= 3 V ± 10%
Ta =
−20°~85°C
Ta = 25°C
Ta =
−20°~85°C
 5
  0.6 µA
 6
Ta = 25°C
VCCs
= 3.3 V ± 0.3 V Ta =
−20°~85°C
  0.7
 7
IACC
High-Voltage Input Current for
WP/ACC
8.5 V ≤ VACC ≤ 9.5 V
  20 mA
(1) If the address remains unchanged for 150 ns, the device will enter Automatic Sleep Mode.
(2) In Standby Mode, with CE1S ≥ VCCs − 0.2 V, these limits are guaranteed when CE2S ≥ VCCs − 0.2 V or CE2S ≤ 0.2 V, and
CIOS ≥ VCCs − 0.2 V or CIOS ≤ 0.2 V.
2001-10-25 15/50