TMP86FS49AIFG Datasheet, PDF (220/296 Pages) Toshiba Semiconductor – 8 Bit Microcontroller

16. Serial Bus Interface(I2C Bus) Ver.-D (SBI)
16.5 I2C Bus Control
TMP86FS49AIFG
When the AL is set to “1”, the MST and TRX are cleared to “0” and the mode is switched to a slave receiver
mode. Thus, the serial bus interface circuit stops output of clock pulses during data transfer after the AL is set
to “1”.
The AL is cleared to “0” by writing data to the SBIDBR, reading data from the SBIDBR or writing data to
the SBICRB.
Master A
SCL pin
SDA pin
Master B
SCL pin
SDA pin
123456789
123
D7A D6A D5A D4A D3A D2A D1A D0A
D7A’ D6A’ D5A’
12
D7B D6B
345678 9
Stop clock output
Releasing SDA pin and SCL pin to high level as losing arbitration.
AL
MST
TRX
Accessed to SBIDBR or SBICRB
INTSBI
Figure 16-8 Example of when a Serial Bus Interface Circuit is a Master B
16.5.11Slave address match detection monitor
In the slave mode, the AAS (Bit2 in SBISRB) is set to “1” when the received data is “GENERAL CALL” or
the received data matches the slave address setting by I2CAR with an address recognition mode (ALS = 0).
When a serial bus interface circuit operates in the free data format (ALS = 1), the AAS is set to “1” after
receiving the first 1-word of data.
The AAS is cleared to “0” by writing data to the SBIDBR or reading data from the SBIDBR.
16.5.12GENERAL CALL detection monitor
The AD0 (Bit1 in SBISRB) is set to “1” when all 8-bit received data is “0” immediately after a start condi-
tion in a slave mode. The AD0 is cleared to “0” when a start or stop condition is detected on a bus.
16.5.13Last received bit monitor
The SDA line value stored at the rising edge of the SCL line is set to the LRB (Bit0 in SBISRB). In the
acknowledge mode, immediately after an INTSBI interrupt request is generated, an acknowledge signal is read
by reading the contents of the LRB.
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