TMPR3916 Datasheet, PDF (204/225 Pages) Toshiba Semiconductor – 32-Bit TX System RISC TX39 Family TMPR3916

Chapter 11 Electrical Characteristics
11.5 Standby Mode Timing
To resume the PLL circuit operations, set the PLLOFF* pin to “High” and the CLKEN pin to high. At
that time, a period of 500 µs is required for the PLL circuit oscillation to stabilize. The following diagram
shows the corresponding timing:
SYSCLK
CLKEN
PLLOFF*
min 500 µs
PLLSTOP
PLL oscillation
Figure 11.5.1 Standby Mode Waveform
11.6 Boot Device
By using the following application circuit, the user can choose between 16 bit and 32 bit boot device.
VSS
Jumper
Jumper connected to ...
VCC => Boot by 16 Bit device
VCC _{VSS => Boot by 32 Bit device}
R = 47 KΩ
A26
TMPR3916
Memory
Device
Figure 11.6.1 Applying External Boot Mode Selection Circuit
11-5
Preliminary