TMPR3916 Datasheet, PDF (125/225 Pages) Toshiba Semiconductor – 32-Bit TX System RISC TX39 Family TMPR3916

Chapter 7 CAN Module (TXCAN)
7.2.1
Mailbox Structure
The following picture shows the structure of the mailbox RAM:
Address
D7
D6
D5
D4
0x0FC
D3
D2
D1
D0
Mailbox 15
TSV1 TSV0
MCF
0x0F8
0x0F4
ID3
ID2
ID1
ID0
0x0F0
Mailbox 0
D7
D6
D5
D4
D3
D2
D1
D0
TSV1 TSV0
MCF
ID3
ID2
ID1
ID0
31 24 23 16 15 8 7
0
Byte 3 Byte 2 Byte 1 Byte 0
Halfword 1
Halfword 0
Word
0x00C
0x008
0x004
0x000
Figure 7.2.1 Mailbox RAM Structure
Each mailbox consists of 16 bytes. The first 4 bytes ID0 to ID3 contain the identifier. Byte 4 (MCF)
contains the message control field and byte 5 is unused. Byte 6 and 7 are reserved for the time stamp
value TSV of an implemented free running counter that indicates when a message was received or
transmitted. The data field consists of the bytes D0 to D7.
One mailbox includes the following data:
• 29 bit identifier, 11 bit base ID and 18 bit extended ID (ID0-ID3)
• identifier extension bit (IDE) (ID3, bit 7)
• global (local) acceptance mask enable bit GAME (LAME) (ID3, bit 6)
• remote frame handling bit RFH (ID3, bit 5)
• remote transmission request bit (RTR) (MCF, bit 4)
• data length code (DLC) (MCF, bit 0-3)
• up to eight bytes for the data field (D0-D7)
• two bytes for the time stamp value (TSV)
7-4
Preliminary