SSM3J306T Datasheet, PDF (2/6 Pages) Toshiba Semiconductor – Power management switch Applications

Switching Time Test Circuit
(a) Test circuit
0
IN
−4 V
10 μs
V_DD = −15 V
R_G = 10 Ω
D.U. ^<= 1%
V_IN: t_r, t_f < 5 ns
Common Source
Ta = 25°C
OUT
R_L
V_DD
SSM3J306T
(b) V_IN
0V
(c) V_OUT
−4 V
V_{DS (ON)}
V_DD
10%
90%
90%
10%
t_r
t_f
t_on
t_off
Marking
3
Equivalent Circuit (top view)
3
JJ9
1
2
1
2
Precaution
V_th can be expressed as the voltage between gate and source when the low operating current value is I_D = −1 mA for
this product. For normal switching operation, V_{GS (on)} requires a higher voltage than V_th and V_{GS (off)} requires a lower
voltage than V_th.
(The relationship can be established as follows: V_{GS (off)} < V_th < V_{GS (on).})
Take this into consideration when using the device.
Handling Precaution
When handling individual devices that are not yet mounted on a circuit board, make sure that the environment is
protected against electrostatic discharge. Operators should wear antistatic clothing, and containers and other objects that
come into direct contact with devices should be made of antistatic materials.
2
2007-11-01