TMP91CW18A Datasheet, PDF (196/278 Pages) Toshiba Semiconductor – Original CMOS 16-Bit Microcontroller

TMP91CW18A
3.11.6 Data Transfer in I²C Bus Mode
(1) Device initialization
Set SBI0BR11<P4EN> and SBI0CR11<ACK, SCK2:0> to 1. Set SBI0BR11 to 1 and
clear bits 7, 6, 5 and 3 of SBI0CR1 to 0.
Set a slave address in I2C0AR1<SA6:0> and I2C0AR<ALS>. (I2C0AR<ALS> = 0
when an addressing format.)
For specifying the default setting to a slave receiver mode, clear the <MST, TRX,
BB> to 0 and set the <PIN> to 1, the <SBIM1:0> to 10.
(2) Start condition generation and slave address generation
1. Master mode
In master mode, the start condition and the slave address are generated as follows.
Check a bus free status (when <BB> = 0).
Set SBI0CR11<ACK> to 1 (Acknowledge mode) and specify a slave address and a
direction bit to be transmitted to the SBI0DBR1.
If SBI0CR11<BB> = 0, the start condition is generated by writing 1111 to
SBI0CR21<MST, TRX, BB and PIN>. Subsequently to the start condition, 9 clocks are
output from the SCL pin. While 8 clocks are output, the slave address and the direction
bit which are set to the SBI0DBR1. On the 9th clock pulse the SDA line is released and
the acknowledge signal is received from the slave device.
An INTI2C1 interrupt request occurs on the falling edge of the 9th clock pulse.
SBI0CR21<PIN> is cleared to 0. In master mode the SCL pin is pulled low while
SBI0CR21<PIN> is 0. When an interrupt request occurs, the value of
SBI0CR21<TRX> is changed according to the direction bit setting only if the slave
device returns an acknowledge signal.
2. Slave mode
In slave mode the start condition and the slave address are received.
After the start condition has been received from the master device, while 8 clocks are
output from the SCL pin, the slave address and the direction bit which are output from
the master device are received.
When a GENERAL CALL or an address matching the slave address set in I2C0AR1
is received, the SDA line is pulled down low on the 9th clock pulse and an acknowledge
signal is output.
An INTI2C1 interrupt request occurs on the falling edge of the 9th clock pulse.
SBI0CR21<PIN> is cleared to 0. In slave mode the SCL line is pulled low while
SBI0CR21<PIN> = 0. When an interrupt request occurs, the value of SBI0CR21<TRX>
is changed according to the direction bit setting only if the slave device returns an
acknowledge signal.
SCL
1
2
3
4
5
6
7
8
9
SDA
<PIN>
INTI2C1
interrupt request
A6
A5
Start condition
A4
A3
A2
A1
Slave address + Direction bit.
A0
R/ W ACK
Acknowledge
signal from a
slave device.
Output of master
Output of slave
Figure 3.11.13 Start Condition Generation and Slave Address Transfer
91CW18A-194
2005-08-15