TA1383AFG Datasheet, PDF (15/47 Pages) Toshiba Semiconductor – NTSC Chroma Decoder, Multi-Point Scan Sync Processor, H/V Frequency Counter IC for Color TV

Data Transmit Format 1
TA1383AFG
S Slave address
7-bit
MSB
S: Start condition
0A
Sub address
8-bit
MSB
A: Acknowledgement
A Transmit data
8-bit
MSB
AP
P: End condition
Data Transmit Format 2
S Slave address 0 A Sub address A Transmit data 1 A ･･････
･･････ Sub address A Transmit data n A P
Data Receive Format
S Slave address
7-bit
MSB
1 A Receive data 1
8-bit
MSB
A Receive data 2
MSB
AP
To receive data, the master transmitter changes to the receiver immediately after the first
acknowledgement. The slave receiver changes to the transmitter.
The end condition is always created by the master.
Optional Data Transmit Format
Auto Increment Mode 1
S Slave address
7- bit
MSB
0A1
Sub address
7-bit
MSB
A Transmit data
8-bit
MSB
Auto Increment Mode 2
S Slave address
7-bit
MSB
0A1
Sub address
7-bit
MSB
A Transmit data 1
8-bit
MSB
････ Transmit data n
8-bit
MSB
AP
In this way, sub addresses are automatically incremented from the specified sub address and data are
set.
15
2005-09-05