TMP91C820A Datasheet, PDF (131/360 Pages) Toshiba Semiconductor – Original CMOS 16-Bit Microcontroller

TMP91C820A
Table 3.7.3 PWM Cycle
at fc = 36 MHz, fs = 32.768 kHz
Select
Select
PWM cycle
system prescaler Gear value
2⁶
2⁷
2⁸
clock
clock <GEAR2:0>
<SYSCK> <PRCK1:0>
φT1 φT4 φT16 φT1 φT4 φT16 φT1
φT4
φT16
1 (fs)
0 (fc)
00
(f_FPH)
XXX
000 (fc)
001 (fc/2)
010 (fc/4)
011 (fc/8)
100 (fc/16)
15.6 ms 62.5 ms 250 ms 31.3 ms 125 ms 500 ms 62.5 ms 250 ms 1000 ms
14.2 μs 56.8 μs 227 μs 28.4 μs 113μs 455 μs 56.8 μs 227 μs 910 μs
28.4 μs 113 μs 455 μs 56.8 μs 227 μs 910 μs 113 μs 455 μs 1820 μs
56.8 μs 227 μs 910 μs 113 μs 455 μs 1820 μs 227 μs 910 μs 3640 μs
113 μs 455 μs 1820 μs 227 μs 910 μs 3640 μs 455 μs 1820 μs 7281 μs
227 μs 910 μs 3640 μs 455 μs 1820 μs 7281 μs 910 μs 3640 μs 14563 μs
10
(fc/16
Clock)
XXX
227 μs 910 μs 3640 μs 455 μs 1820 μs 7281 μs 910 μs 3640 μs 14563 μs
XXX: Don’t care
(5) Settings for each mode
Table 3.7.4 shows the SFR settings for each mode.
Register Name
<Bit Symbol>
Function
8-bit timer × 2 channels
16-bit timer mode
8-bit PPG × 1 channel
8-bit PWM × 1 channel
8-bit timer × 1 channel
−: Don’t care
Table 3.7.4 Timer Mode Setting Registers
TA01MOD
TA1FFCR
<TA01M1:0>
<PWM01:00>
<TA1CLK1:0>
<TA0CLK1:0>
TA1FFIS
Timer Mode
00
01
10
11
11
PWM Cycle
−
−
−
2⁶, 2⁷, 2⁸
(01, 10, 11)
−
Upper Timer Input
Clock
Lower timer
match
φT1, φT16, φT256
(00, 01, 10, 11)
−
−
−
φT1, φT16, φT256
(01, 10, 11)
Lower Timer
Input Clock
Timer F/F Invert Signal
Select
External clock
φT1, φT4, φT16
(00, 01, 10, 11)
0: Lower timer output
1: Upper timer output
External clock
φT1, φT4, φT16
(00, 01, 10, 11)
External clock
φT1, φT4, φT16
(00, 01, 10, 11)
External clock
φT1, φT4, φT16
(00, 01, 10, 11)
−
−
−
−
Output disabled
91C820A-129
2006-01-31