TA1318AFG Datasheet, PDF (13/42 Pages) Toshiba Semiconductor – SYNC Processor, Frequency Counter IC for TV Component Signals

TA1318AFG
Bus Control Map
Write Mode
Slave Address: D8/DA/DC_H
D7
Sub-Add
MSB
D6
D5
D4
00
H-FREQUENCY
HD1/VD1-OUT SW
01
DAC1
DAC2
02
V-FREQUENCY
CLP-PHS
03
HD PHASE
D3
D2
HD2/VD2-OUT SW
DAC3
TEST
FREQ DET SW
D0
D1
LSB
SEPA LEVEL
HD1-INV HD2-INV
INPUT SW
VD1-INV VD2-INV
Preset
MSB LSB
1000 0000
1000 0000
1000 0000
1000 0000
Read Mode
Slave Address: D9/DB/DD_H
D7
MSB
D6
D5
0
POR
1
HD-IN
D4
D3
D2
V FREQUENCY DET
H FREQUENCY DET
D1
D0
LSB
Bus Control Functions
Write Mode (*: Preset)
• H-FREQUENCY (Horizontal oscillation frequency)
Switches horizontal frequency.
(00): 15.75 kHz (01): 31.5 kHz
*(10): 33.75 kHz (11): 45 kHz
Note: To prevent a horizontal mislock, set (10) 33.75 kHz mode just before (01) 31.5 kHz mode setting when
the horizontal frequency mode is switched to (01) 31.5 kHz mode.(wait time: 1 ms or more)
Additionally, in 31.5 kHz mode, set (10) 33.75 kHz mode at first and set (01) 31.5 kHz mode again,
when 525 p/625 p signal is pulled-in again from no-input.
• HD1/VD1-OUT SW (HD1/VD1 output switch)
Switches output from pin 16/28. When set to 00, 01, or 10, outputs HD/VD without synchronization.
When set to 11, outputs HD/VD from the sync circuit. (Note) Synchronized VD width will change, when
HD PHASE will be changed.
*(00): HD1/VD1 (01): HD2/VD2
(10): HD3/VD3 (11): Synchronized HD/VD
• HD2/VD2-OUT SW (HD2/VD2 output switch)
Switches output from pin 19/29. When set to 00, 01, or 10, outputs HD/VD without synchronization.
When set to 11, outputs HD/VD from the sync circuit. (Note) Synchronized VD width will change, when
HD PHASE will be changed.
*(00): HD1/VD1 (01): HD2/VD2
(10): HD3/VD3 (11): Synchronized HD/VD
• SEPA LEVEL (Sync separation level switch)
Switches sync separation level of pin 24/26. Set values are the levels from sync tip. Sync separation level
is changed according to the ratio of H-SYNC width during 1H period.
*(00): 10IRE
(01): 15IRE
(10): 20IRE
(11): 25IRE (at 1125I/60)
• DAC1 (DAC1 control)
Controls 2-bit DAC (pin 12).
(00): 1 V
(01): 3 V
*(10): 5 V
(11): 7 V
• DAC2 (DAC2 control)
Controls 2-bit DAC (pin 25).
*(00): 1 V
(01): 3 V
(10): 5 V
(11): 7 V
• DAC3 (DAC3 control)
Controls open collector 1-bit DAC (pin 30).
*(0): OPEN (HIGH)
(1): ON (LOW)
13
2006-02-27