TMP86CH72FG Datasheet, PDF (126/198 Pages) Toshiba Semiconductor – 8 Bit Microcontroller

12. Synchronous Serial Interface (SIO)
12.3 Function
TMP86CH72FG
SIOS
SIOF
SEF
SCK pin
SI pin
A₇
RXF
INTSIO
SIOS = "0" causes the SIO
to stop transferring.
C₆ C₅ C₄ C₃ C₂ C₁ C₀ D₇ D₆ D₅ D₄ D₃ D₂ D₁ D₀
Clearing SIOS within the interrupt service routine
Figure 12-10 SIOCR1<SIOS> Clear Timing
All data bytes
have been
read from
SIOBUF.
12.3.3.4 Receive error
During operation on an external clock, the following case is detected as a receive error, causing the
receive error flag (SIOSR<RXERR>) to be set to “1”. If a receive error occurs, discard all data from the
receive buffer.
• If the reception of the next data byte ends with SIOBUF full (SIOSR<RXF> = “1”) (if eight clock
pulses are supplied to the SCK pin)
If a receive error is detected, be sure to set SIOCR1<SIOINH> to “1” to force the SIO to halt. Setting
SIOCR1<SIOINH> to “1” initializes the SIOCR1<SIOS> and SIOSR registers; no other registers or bits
are initialized.
Note: When the SIO is running on an external clock, it becomes impossible to read the content of the receive
data buffer (SIOBUF) correctly if the SCK pin goes low before as many data bytes as specified in
SIOCR2<SIORXD> are read.
A receive error flag (SIOSR<RXF>) can be set only after eight clock pulses are input upon completion
of reception. If only one to seven transfer clock pulses (including noise) are input to the SCK pin, there-
fore, it becomes impossible to determine whether the pulses at the pin are those unnecessary. So, it is
recommended that the system employ a backup method such as checksum-based verification.
Before restarting reception, be sure to force the SIO to halt (SIOCR1<SIOINH> = “1”).
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