TA1322FN Datasheet, PDF (12/21 Pages) Toshiba Semiconductor – DOWB-CONVERTER IC WITH PLL FOR SATELLITE TUNER

the output is ON (normal mode); when set to [1], the output is OFF.
TA1322FN
[[BYTE 5]]
Byte 5 can be used to set control the output port.
Bit 1 (P7), bit 3 (P5) and bit 4 (P4) are used to control output port P7, P5 and P4.
Bit 2 (P6) is used to control change IF output port. When bit 2 is set to [0], IF output 1 (pin 19)
is ON; when set to [1], IF output 1 (pin 21) is ON.
Bit 8 (P0) is used to control band output port (P0). When bit 8 is set to [0], P0 is OFF; when set
to [1], P0 is ON. (P0) output port can be driven at less than 40 mA.
B) READ mode (status request)
When READ mode is set, power-on reset operation status, phase comparator lock detector output
status, comparator input voltage status are output to the master device.
Bit 1 (POR) indicates the power-on reset operation status. When the power supply of VCC2 stops,
bit is set to [1]. The condition for reset to [0], voltage supplied to VCC2 is 3 V or higher, transmission
is requested in READ mode, and the status is output. (when VCC2 is turned on, bit 1 is also set to [1].)
Bit 2 (FL) indicates the phase comparator lock status. When locked, [1] is output; when unlocked,
[0] is output.
Bit 3 (IP7), bit 4 (IP5) and bit 5 (IP4) indicate the input comparator status. High level status is
output [1], low level status is output is [0]. When voltage applied from 0 V to 1.5 V, output is [0].
When from 2.7 V to 6 V, output is [1].
Data Format
A) Write mode
MSB
LSB
1 Address Byte
2 Divider Byte 1
3 Divider Byte 2
4 Control Byte
5 Band SW Byte
1
1
0
0
0
MA1
MA0 R/W = 0 ACK
0
N14
N13
N12
N11
N10
N9
N8
ACK
N7
N6
N5
N4
N3
N2
N1
N0 ACK (L)
1
CP
T1
T0
TS2
TS1
TS0
OS ACK (L)
P7
P6
P5
P4
´
´
´
P0 ACK (L)
´: Don’t care
ACK: Acknowledged
(L): Latch and transfer timing
B) Read mode
MSB
LSB
1 Address Byte
1
1
0
0
0
MA1
MA0 R/W = 1 ACK
2 Status Byte
POR
FL
IP7
IP5
IP4
1
1
1
¾
ACK: Acknowledged
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2002-02-12