TA1322FN Datasheet, PDF (11/21 Pages) Toshiba Semiconductor – DOWB-CONVERTER IC WITH PLL FOR SATELLITE TUNER

TA1322FN
PLL Block
--I²C Bus Communications Control--
The TA1322FN conforms to Standard Mode I²C bus format.
I²C Bus Mode allows two-way bus communication using Write Mode (for receiving data) and Read Mode (for
processing status data).
Write Mode or Read Mode can be selected by setting the least significant bit (R/W bit) of the address byte.
If the least significant address bit is set to 0, Write Mode is selected; if it is set to 1, Read Mode is selected.
Address can be set using the hardware bits. 4 programmable address can be programmed.
Using this setting, multiple frequency synthesizers can be used on the same I²C bus line.
The address for the hardware bit setting can be selected by applying voltage to the address setting pin (ADR-pin
18). The address is selected according to the setting of these bits.
During acknowledgment of receipt of a valid address byte, the serial data (SDA) line is Low.
If Write Mode is currently selected, when the data byte is programmed, the serial data (SDA) line will be Low
during the next acknowledgment.
A) Write mode (setting command)
When Write Mode is selected, byte 1 holds address data; byte 2 and byte 3 hold frequency data; byte
4 holds the divider ratio setting and function setting data; and byte 5 holds output port data.
Data is latched and transferred at the end of byte 3, byte 4 and byte 5.
Byte 2 and byte 3 are latched and transferred as a byte pair.
Once a valid address has been received and acknowledged, the data type can be determined by
reading the first bit of the next byte. That is, if the first bit is 0, the data is frequency data; if it is 1,
the data is function-setting or band output data.
Additional data can be input without the need to transmit the address data again until the I²C bus
STOP condition is detected (e.g. a frequency sweep using additional frequency data is possible).
If a data transmission is aborted, data programmed before the abort remains valid.
[[BYTE 1]]
The address data for byte 1 can be set using the hardware bit.
The hardware bit can be set by applying a voltage to the address-setting pin (ADR: pin 18).
[[BYTE 2, BYTE 3]]
Byte 2, byte 3 control the 15-bit programmable counter ratio and are stored in the 15-bit shift
register together with frequency setting counter data.
The program frequency can be calculated using the following formula:
fosc = 2 ´ fr ´ N
fosc: Program frequency
fr: Phase comparator reference frequency
N: Counter total divider ratio
fr is calculated from the crystal oscillator frequency and the reference frequency divider ratio
set in byte 4 (the control byte).
(fr = X’tal oscillator frequency/reference divider ratio)
The reference frequency divider ratio can be set to 1/64 or 1/128.
When a 4-MHz crystal oscillator is used, fr = 62.5 kHz or 31.25 kHz. The respective step
frequencies are 125 kHz and 62.5 kHz.
[[BYTE 4]]
Byte 4 is a control byte used to set function. Bit 2 (CP) controls the output current of the
charge-pump circuit.
When bit 2 is set to [0], the output current is set to ±50 mA; when set to [1], ±240 mA.
Bit 3 (T1) is used to set the test mode. When bit 3 is set to [0], normal mode; when set to [1],
test mode.
Bit 4 (T0) is used to set the charge pump. When bit 4 is set to [0], charge pump is ON (normal
used); When set to [1], charge pump is OFF.
Bit 5 (TS2) and bit 6 (TS1) used to set the test mode. They are used to set the charge pump test,
phase comparator reference signal output, and 1/2 counter divider ratios.
Bit 7 (TS0) is used to set the X’tal reference frequency divider ratio. When bit 7 is set to [0],
1/128 (frequency step is 62.5 kHz); when set to [1], 1/64 (frequency step is 125 kHz).
Bit 8 (OS) is used to set the charge pump drive amplifier output setting. When bit 8 is set to [0],
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2002-02-12