TMP91FW60FG Datasheet, PDF (118/322 Pages) Toshiba Semiconductor – 16 Bit Microcontroller

TMP91FW60
6.4.2 16-bit timer mode
A 16-bit interval timer is configured by pairing the two 8-bit timers TMRA0 and TMRA1.
To make a 16-bit interval timer in which TMRA0 and TMRA1 are cascaded together, set
TA01MOD<TA01M1:0> to 01.
In 16-bit timer mode, the overflow output from TMRA0 is used as the input clock for TMRA1, regardless of
the value set in TA01MOD<TA1CLK1:0>. Table 6-2 shows the cycle of the input clock for TMRA0.
LSB 8-bit set to TA0REG and MSB 8-bit is for TA1REG. Please keep setting TA0REG first because setting
data for TA0REG inhibit its compare function and setting data for TA1REG permit it.
Example: To generate an INTTA1 interrupt every 0.4 [s] at fc = 20 MHz, set the timer registers TA0REG
and TA1REG as follows:
* Clock state
System clock
Prescaler clock
Clock gear
: High frequency (fc)
: f_FPH
: 1 (fc)
If φT16 (2⁷/fc μs at fc = 20 MHz) is used as the input clock for counting, set the following value in the regis-
ters: 0.4 s/(2⁷/fc) μs ≒ 62500 = F424H (e.g., set TA1REG to F4H and TA0REG to 24H). As a result, INTTA1
interrupt can be generated every 0.4 [s].
The comparator match signal is output from TMRA0 each time the up counter UC0 matches TA0REG,
though the up counter UC0 is not cleared and also INTTA0 is not generated.
In the case of the TMRA1 comparator, the match detect signal is output on each comparator pulse on which
the values in the up counter UC1 and TA1REG match.
When the match detect signal is output simultaneously from both the comparators TMRA0 and TMRA1, the
up counters UC0 and UC1 are cleared to 0 and the interrupt INTTA1 is generated. Also, if inversion is enabled,
the value of the timer flip-flop TA1FF is inverted.
Example: When TA1REG = 04H and TA0REG = 80H
Value of up counter
(UC1, UC0)
TMRA0 comparator
match detect signal
TMRA1 comparator
match detect signal
Interrupt INTTA0
Interrupt INTTA1
0080H 0180H 0280H 0380H 0480H 0080H
Timer output TA1OUT
Inversion
Figure 6-7 Timer Output by 16-Bit Timer Mode
Page 114
2007-10-15