TMP88CS38 Datasheet, PDF (118/226 Pages) Toshiba Semiconductor – 8-bit single chip microcomputer

TMP88CS38/CM38A/CP38A
(2) 8-bit receive end interrupts and measurement modes
By determining one-cycle remote control signal as one-bit data set to “0” or one-pulse
width remote control signal as one-bit data set to “1”, an INT3 request is generated
after 8-bit data is received. When “0” is determined, this means the upper four bits in
the 8-bit up counter have not reached the CREGA value. When “1” is determined, this
means the upper four bits in the 8-bit up counter have reached or exceeded the CREGA
value. The 8-bit up counter value is saved in RXCTR after one bit is determined. The
determined data is saved, bit by bit, in RXDBR at the rising edge of the remote control
signal (when RPOLS = 1, falling edge). The number of bits saved in RXDBR is counted
by the receive bit counter and saved in RBCTM. RBCTM is set to “0001B” at the rising
edge of the input (when RPOLS = 1, falling edge) after the INT3 request is generated.
RNCM
RCCK
8-bit
up counter value
RCS
FE
FF
1
Set to “1” by command.
OVFF
Receive bit
counter value* ^{n − 1 n}
RBCTM* n − 1 n
INT3
request
*: Valid only when 8 bits are received.
Figure 2.10.7 Overflow Interrupt Timing Chart
88CS38-118
2007-09-12