TC55W1600FT Datasheet, PDF (11/13 Pages) Toshiba Semiconductor – 1,048,576-WORD BY 16-BIT/2,097,152-WORD BY 8-BIT FULL CMOS STATIC RAM

TC55W1600FT-55,-70
DATA RETENTION CHARACTERISTICS (Ta = −40° to 85°C)
SYMBOL
PARAMETER
MIN
V_DH
Data Retention Supply Voltage
1.5
I_DDS2
V_DH = 3.1 V Ta = −40~85°C

Standby Current
Ta = −40~40°C

V_DH = 3.0 V
Ta = −40~85°C

t_CDR
t_R
Chip Deselect to Data Retention Mode Time
Recovery Time
0
t_RC(See ^Note)
Note: Read cycle time
TYP






MAX
3.1
10
1
5


UNIT
V
µA
ns
ns
CE1, UB / LB CONTROLLED DATA RETENTION MODE ^{(See Note 1,4)}
V_DD
2.3 V
V_DD
DATA RETENTION MODE
V_IH
CE1
or UB / LB
GND
(See Note 2)
t_CDR
V_DD − 0.2 V
CE2 CONTROLLED DATA RETENTION MODE ^{(See Note 3)}
V_DD
V_DD
2.3 V
CE2
V_IH
V_IL
GND
t_CDR
DATA RETENTION MODE
0.2 V
(See Note 2)
t_R
t_R
Note:
(1)
(2)
(3)
(4)
In CE1 or UB / LB controlled data retention mode, minimum standby current mode is entered when
CE2 ≤ 0.2 V or CE2 ≥ VDD − 0.2 V.
When CE1 or UB / LB is operating at the VIH minimum level, the operating current is given by IDDS1
during the transition of VDD from 3.1 V to 2.4 V.
In CE2 controlled data retention mode, minimum standby current mode is entered when CE2 ≤ 0.2 V.
In UB / LB controlled data retention mode, minimum standby current mode is entered when CE1 /CE2
≤ 0.2 V or CE1 /CE2 ≥ VDD − 0.2 V.
2002-02-12 11/13