TC74HC259AP_07 Datasheet, PDF (1/10 Pages) Toshiba Semiconductor – 8-Bit Addressable Latch

TC74HC259AP/AF/AFN
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74HC259AP,TC74HC259AF,TC74HC259AFN
8-Bit Addressable Latch
The TC74HC259A is a high speed CMOS ADDRESSABLE
LATCH fabricated with silicon gate C²MOS technology.
It achieve the high speed operation similar to equivalent
LSTTL while maintaining the CMOS low power dissipation.
The respective bits are controlled by address inputs A, B, and
C. When CLEAR input is held high and enable input G is held
low, the data is written into the bit selected by address inputs,
the other bit hold their previous conditions.
When both CLEAR and G held high, writing of all bits is
inhibited regardless of adress inputs, and their previous
condition are held. When CLEAR is held low and G is held
high, all bits are resent to low regardless of the other inputs.
When both of CLEAR and G held low, all bits which isn’t
selected by adress inputs are resent to low.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
Features
• High speed: t_pd = 15 ns (typ.) at V_CC = 5 V
• Low power dissipation: I_CC = 4 μA (max) at Ta = 25°C
• High noise immunity: V_NIH = V_NIL = 28% V_CC (min)
• Output drive capability: 10 LSTTL loads
• Symmetrical output impedance: |I_OH| = I_OL = 4 mA (min)
• ^{Balanced propagation delays: t}pLH ^{∼− t}pHL
• Wide operating voltage range: V_CC (opr) = 2~6 V
• Pin and function compatible with 74LS259
Pin Assignment
Note: xxxFN (JEDEC SOP) is not available in
Japan.
TC74HC259AP
TC74HC259AF
TC74HC259AFN
Weight
DIP16-P-300-2.54A
SOP16-P-300-1.27A
SOL16-P-150-1.27
: 1.00 g (typ.)
: 0.18 g (typ.)
: 0.13 g (typ.)
1
2007-10-01