TC74HC237AP_07 Datasheet, PDF (1/9 Pages) Toshiba Semiconductor – 3-to-8 Line Decoder/Latch

TC74HC237AP/AF
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74HC237AP,TC74HC237AF
3-to-8 Line Decoder/Latch
The TC74HC237A is a high speed CMOS 3-to-8 LINE
DECODER ADDRESS LATCH fabricated with silicon gate
C2MOS technology.
It achieves the high speed operation similar to equivalent
LSTTL while maintaining the CMOS low power dissipation.
It is composed of a 3-bit input latches with a common GL
enable input and 3-to-8 line decoder with enable inputs G1 and
G2 . The 3-bit binary data is stored into the input latch on the
high level of GL . The value of this data determines which one of
the outputs will go low.
When the enable input G1 is held low or G2 is held high,
decoding function is inhibited and all the 8 outputs go high. The
two enable inputs are provided to ease cascade connection and
permits the application address decoder for memory system.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
Features
• High speed: t_pd = 12 ns (typ.) at V_CC = 5 V
• Low power dissipation: I_CC = 4 μA (max) at Ta = 25°C
• High noise immunity: V_NIH = V_NIL = 28% V_CC (min)
• Output drive capability: 10 LSTTL loads
• Symmetrical output impedance: |I_OH| = I_OL = 4 mA (min)
• Balanced propagation delays: t_pLH ^∼− t_pHL
• Wide operating voltage range: V_CC (opr) = 2~6 V
• Pin and function compatible with 74LS237
Pin Assignment
TC74HC237AP
TC74HC237AF
Weight
DIP16-P-300-2.54A
SOP16-P-300-1.27A
: 1.00 g (typ.)
: 0.18 g (typ.)
1
2007-10-01