TC58NYG0S3EBAI4 Datasheet, PDF (1/65 Pages) Toshiba Semiconductor – TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

TC58NYG0S3EBAI4
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
1 GBIT (128M × 8 BIT) CMOS NAND E²PROM
DESCRIPTION
The TC58NYG0S3E is a single 1.8V 1 Gbit (1,107,296,256 bits) NAND Electrically Erasable and Programmable
Read-Only Memory (NAND E²PROM) organized as (2048 + 64) bytes × 64 pages × 1024blocks.
The device has two 2112-byte static registers which allow program and read data to be transferred between the
register and the memory cell array in 2112-byte increments. The Erase operation is implemented in a single block
unit (128 Kbytes + 4 Kbytes: 2112 bytes × 64 pages).
The TC58NYG0S3E is a serial-type memory device which utilizes the I/O pins for both address and data
input/output as well as for command inputs. The Erase and Program operations are automatically executed making
the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still
cameras and other systems which require high-density non-volatile memory data storage.
FEATURES
• Organization
x8
Memory cell array 2112 × 64K × 8
Register
2112 × 8
Page size
2112 bytes
Block size
(128K + 4K) bytes
• Modes
Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy,
Multi Page Program, Multi Block Erase, Multi Page Copy, Multi Page Read
• Mode control
Serial input/output
Command control
• Number of valid blocks
Min 1004 blocks
Max 1024 blocks
• Power supply
V_CC = 1.7V to 1.95V
• Access time
Cell array to register 25 µs max
Serial Read Cycle 25 ns min (CL=30pF)
• Program/Erase time
Auto Page Program
Auto Block Erase
300 µs/page typ.
2.5 ms/block typ.
• Operating current
Read (25 ns cycle)
Program (avg.)
Erase (avg.)
Standby
30 mA max.
30 mA max
30 mA max
50 µA max
• Package
P-TFBGA63-0911-0.80CZ (Weight: 0.15 g typ.)
1
2011-03-01C