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| XC25BS8 Datasheet, PDF (8/14 Pages) Torex Semiconductor – Ultra Small PLL Clock Generator ICs with Built-In Divider/Multiplier Circuits | |||
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XC25BS8Series
ËNOTE ON USE (Continued)
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ËInstructions on Pattern Layout
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1. In order to stabilize VDD voltage level, we recommend that a by-pass capacitor (CIN) be connected as close as possible to
the VDD and VSS pins.
2. Please mount the low pass filter capacitor C1(=0.1ÐF) as close to the IC as possible.
3. Make the pattern as close to the IC as possible and use thick, short connecting traces to reduce the circuit impedance.
4. Make sure that the VSS (GND) traces are as thick as possible, as variations in ground potential caused by noise may
result in instability of this product.
< Reference pattern layout >
* We prepare the evaluation board PCB, which is designed by the below layout pattern.
1. SOT-26W Reference Pattern Layout
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QO
CE
2. USP-6C Reference Pattern Layout
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VDD
VSS
C1
CLK
TOREX XC25BS8
8/14
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