XC25BS8 Datasheet, PDF (5/14 Pages) Torex Semiconductor – Ultra Small PLL Clock Generator ICs with Built-In Divider/Multiplier Circuits

XC25BS8
Series
˙ELECTRICAL CHARACTERISTICS (Continued)
˔Recommended Operating Conditions: XC25BS8001xx (610 multiplication, Input 15kHz (TYP.)) 5.0V (TYP.)
Tested below Ta=25^OC
PARAMETER
SYMBOL
CONDITIONS
MIN.
MAX.
UNITS
Supply Voltage 5.0V
Input Frequency
Multiplier Ratio
Output Frequency
Capacity Overload ^(*3)
Output Start Time ^(*2)(*3)
V_DD
f_CLKin
N/M
f_Q0
CL
t_START
5.0V (TYP.) operation
(*1)
Typical value is shown ^(*1)
(*1)
f_CLKin＝14.250kHz
4.50
5.50
14.250
15.750
610
8.693
96.075
-
15
0.05
20
V
kHz
MHz
pF
ms
NOTE:
*1: The values are measured when a capacitor C_IN=0.1ЖF is connected between V_DD and V_SS pins, a capacitor C1=0.1ЖF is connected
between LFP and V_SS pins.
*2: It is a time to get stable output signal from Q0 pin after the CE pin is turned on while applying supply voltage to the V_DD pin and applying
the input signal to the CLKin pin.
*3: Values indicated are design values which are not guaranteed 100%.
˔DC Characteristics: XC25BS8001xx (610 multiplication, Input 15kHz (TYP.) ) 5.0V (TYP.)
PARAMETER
H Level Input Voltage
L Level Input Voltage
H Level Input Current
L Level Input Current
H Level Output Voltage
L Level Output Voltage
Supply Current 1
Supply Current 2
CE H Level Voltage
CE L Level Voltage
CE Pull-Down Resistance 1
CE Pull-Down Resistance 2
Output Off Leak Current
SYMBOL
V_IH
V_IL
Ii_H
Ii_L
V_OH
V_OL
I_DD1
I_DD2
V_CEH
V_CEL
Rdn1
Rdn2
I_OZ
CONDITIONS
V_CLKin=V_DD-0.5V
V_CLKin=0.5V
V_DD=4.50V，IOH=-8mA
V_DD=4.50V，IOL= 8mA
V_DD=5.50V，CE= 5.50V
V_DD=5.50V，CE= 0.0V
CE= V_DD
CE= 0.1*V_DD
V_DD=5.50V，CE= 0.0V
MIN.
4.00
-
-
-5.0
3.60
-
-
-
4.00
-
0.1
2
-
TYP.
-
-
-
-
-
-
4.0
-
-
-
0.4
20
-
MAX.
-
1.00
5.0
-
-
0.65
8.0
20
-
1.00
0.8
40
10
UNITS
V
V
μA
μA
V
V
mA
μA
V
V
MΩ
kΩ
μA
Ta=25ˆ
CIRCUIT
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NOTE:
TEST CONDITION: V_DD=5.0V, f_CLKin=15kHz, C1=0.1ЖF, Multiplier ratio=610, No load
˔AC Characteristics: XC25BS8001xx (610 multiplication, Input 15kHz (TYP.)) 5.0V (TYP.)
Ta=25ˆ
PARAMETER
Output Rise Time ^(*1)
Output Fall Time ^(*1)
Output Signal Duty Cycle ^(*1)
PLL Output Signal Jitter 1 ^(*1)
PLL Output Signal Jitter 2 ^(*1)
SYMBOL
t_R
t_F
Duty
t_J1
t_J２
CONDITIONS
(20% ~ 80%)
(20% ~ 80%)
1М (Output Period)
Peak to Peak (Output Tracking)
MIN. TYP. MAX. UNITS CIRCUIT
-
2.5 5.0
ns
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-
2.5 5.0
ns
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45 50 55
ˋç
ᶃç
-
40
-
ps
ᶃç
- 15.0 -
ns
ᶃç
NOTE:
TEST CONDITION: V_DD=5.0V, fCLKin=15kHz, C1=0.1ЖF, Multiplier ratio=610, CL=15pF
*1: Values indicated are design values, which are not guaranteed 100%.
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