XC25BS7 Datasheet, PDF (6/13 Pages) Torex Semiconductor – PLL Clock Generator ICs with Built-In Divider/Multiplier Circuits

XC25BS̓Series
˙NOTE ON USE
(1) Please use this IC within the stated absolute maximum ratings. The IC is liable to malfunction should the ratings be
exceeded.
(2) The series is an analog IC. Please use a 0.01ЖF to 0.1ЖF of a by-pass capacitor.
(3) Rq0 shown in the Typical Application Circuit is a matching resistor. The use is recommended in order to counter
unwanted radiations.
(4) Please place the by-pass capacitor and the matching resistor as close to the IC as possible. The IC may not operate
normally if the by-pass capacitor is not close enough to the IC. Further, the unwanted radiation may occur between
the resistor and the IC pin if the matching resistor is not close enough to the IC.
(5) When the CE pin is not controlled by external signals, it is recommended that a time constant circuit of R1=1kЊ ʷC1
= 0.1ЖF be added for stability.
(6) With this IC, output is achieved by dividing and multiplying the reference oscillation by means of the PLL circuit. In
cases where this output is further used as a reference oscillation of another PLL circuit, it may be that the final output
signal's jitter increases; therefore, all necessary precautions should be taken to avoid this.
(7) It is recommended that a low noise power supply, such as a series regulator, be used as the series’ supply voltage.
Using a power supply such as a switching regulator may enlarge the jitter, which in turn may lead to abnormal
operation. Please confirm its operation with the actual device.
(8) For operating the IC normally, please take procedures below when applying voltage to the series’ input pin:
1) Apply power source while the CE pin is "L" level with no clock input (high-Impedance or “L”),
2) Input the clock,
3) At least 100Жs after applying clock input, change the CE pin into “H” level and then to enable.
The IC has to be started by inputting the clock once the power rises completely. The CE pin, then, should be enabling.
If the CE pin becomes enable and the clock is inputted before the power rises completely, an internal reset circuit
does not operate normally which may cause to generate extraneous frequency.
(9) As for this IC, synchronization of input and output signals occurs at the rising edge.
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