XC25BS7 Datasheet, PDF (5/13 Pages) Torex Semiconductor – PLL Clock Generator ICs with Built-In Divider/Multiplier Circuits

XC25BS7
Series
˙ELECTRICAL CHARACTERISTICS (Continued)
˔Recommended Operating Conditions: XC25BS7001xx (256 multiplication, Input 48kHz (TYP.)) 3.3V (TYP.)
Tested below Ta=25^OC
PARAMETER
SYMBOL
CONDITIONS
MIN.
MAX.
UNIT
Supply Voltage
Input Frequency
Multiplier/Divider Ratio
Output Frequency
Capacity Overload ^(*3)
Output Start Time ^(*2)(*3)
V_DD
fCLKin
N/M
fQ0
CL
T_ON
3.3V (TYP.) operation
(*1)
Typical value is shown ^(*1)
(*1)
fCLKin＝45kHz
2.97
3.63
45.000
60.000
256
11.520
15.360
-
15
0.05
20
V
kＨｚ
-
MHz
pF
ms
NOTE:
*1: Connected C_IN=0.1ЖF of a ceramic capacitor between the V_DD pin the V_SS pin while testing.
*2: Time until signal via the Q0 pin flows stably from applying supply voltage to the V_DD pin and control voltage to the CE pin while
applying the input signal to the CLKin pin.
*3: The value indicated at output start time is designed values which are not guaranteed values.
˔DC Characteristics: XC25BS7001xx (256 multiplication, Input 48kHz (TYP.) ) 3.3V (TYP.)
PARAMETER
H Level Input Voltage
L Level Input Voltage
H Level Input Current
L Level Input Current
H Level Output Voltage
L Level Output Voltage
Supply Current 1
Supply Current 2
CE H Level Voltage
CE L Level Voltage
CE Pull-Down Resistance 1
CE Pull-Down Resistance 2
Output Off Leak Current
SYMBOL
V_IH
V_IL
Ii_H
Ii_L
V_OH
V_OL
I_DD1
I_DD2
V_CEH
V_CEL
Rdn1
Rdn2
I_OZ
Test Conditions: V_DD=3.3V, fCLKin=48kHz, Multiplier ratio=256, Ta=25ˆ, No Load
CONDITIONS
MIN. TYP. MAX. UNIT CIRCUIT
2.70
-
-
V
①
-
-
0.60
V
①
V_CLKin=V_DD-0.3V
-
-
3.0
μA
②
V_CLKin=0.3V
-3.0
-
-
μA
②
V_DD=2.97V, I_OH=-4mA
2.50
-
-
V
③
V_DD=2.97V, I_OL= 4mA
-
-
0.40
V
③
V_DD=3.63V, CE= 3.63V
-
3.0
6.0
mA
④
V_DD=3.63V, CE= 0.0V
-
-
10
μA
④
2.70
-
-
V
①
-
-
0.45
V
①
CE=V_DD
0.2 1.0
1.8
MΩ
⑤
CE=0.1 x V_DD
10
30
60
kΩ
⑤
V_DD=Q0=3.63V, CE= 0.0V
-
-
10
μA
⑥
˔AC Characteristics: XC25BS7001xx (256 multiplication, Input 48kHz (TYP.)) 3.3V (TYP.)
PARAMETER
Output Rise Time ^(*1)
Output Fall Time ^(*1)
Output Signal Duty ^(*1)
SYMBOL
Tr
Tf
Duty
PLL Output Signal Jitter 1 ^(*1)
T_J1
PLL Output Signal Jitter 2 ^(*1)
T_J２
Test Conditions: V_DD=3.3V, fCLKin=48kHz, Multiplier ratio=256, Ta=25ˆ, CL=15pF
CONDITIONS
MIN. TYP. MAX. UNIT CIRCUIT
(20% ~ 80%)
-
2.5 5.0
ns
①
(20% ~ 80%)
fQ0≦60MＨｚ
fQ0≧60MＨｚ
-
2.5 5.0
ns
①
45 50 55
％
①
40 50 60
％
1σ (Output Period)
-
20
-
ps
①
Peak to Peak (Output Tracking)
-
20
-
ns
①
NOTE:
*1: Values indicated at the AC Characteristics are designing values, which are not guaranteed values.
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