XC61H Datasheet, PDF (5/13 Pages) Torex Semiconductor – Voltage Detector with Delay Circuit Built-In

XC61H
Series
˙OPERATIONAL EXPLANATION
˔CMOS output
ᶃç An input voltage V_IN starts higher than the release voltage VDR. Then, V_IN voltage will gradually fall. When V_IN voltage is
higher than detect voltage VDF, output voltage RESETB is equal to the VIN voltage.
*Note that high impedance exists at RESETB with the N-channel open drain configuration. If the RESETB pin is pulled
up, RESETB will be equal to the pull up voltage.
ᶄ When VIN falls below VDF, RESETB will be equal to ground voltage VSS level (detect state).
* Note that this also applies to N-channel open drain configurations.
ᶅ When VIN falls to a level below that of the minimum operating voltage VMIN, output will become unstable.
*When the output pin is generally pulled up with N-channel open drain configurations, output will be equal to pull up
voltage.
ᶆ When VIN rises above the VSS level (excepting levels lower than minimum operating voltage), RESETB will be equal to
VSS until VIN reaches the VDR level.
ᶇ Although VIN will rise to a level higher than VDR, RESETB maintains ground voltage level via the delay circuit.
ᶈ After taking a release delay time, VIN voltage will be output at the RESETB pin.
ç *High impedance exists with the N-channel open drain configuration and that voltage will be dependent on pull up.
Notes:
1. The difference between VDR and VDF represents the hysteresis width.
2. Release delay time (t_DR) represents the time it takes until when VIN voltage appears at RESETB pin once the input
voltage has exceeded the VDR level.
˔Timing Chart
Output Voltage (RESETB)
Release Delay Time (t_DR)
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