XC61F_1 Datasheet, PDF (4/12 Pages) Torex Semiconductor – Voltage Detectors, Delay Circuit Built-In

XC61F Series
■OPERATIONAL EXPLANATION
●CMOS output
① When a voltage higher than the release voltage (VDR) is applied to the voltage input pin (VIN), the voltage will
gradually fall. When a voltage higher than the detect voltage (VDF) is applied to VIN, output (VOUT) will be equal to the
input at VIN.
Note that high impedance exists at VOUT with the N-channel open drain configuration. If the pin is pulled up, VOUT will
be equal to the pull up voltage.
② When VIN falls below VDF, VOUT will be equal to the ground voltage (VSS) level (detect state). Note that this also
applies to N-channel open drain configurations.
③ When VIN falls to a level below that of the minimum operating voltage (VMIN ) output will become unstable. Because
the output pin is generally pulled up with N-channel open drain configurations, output will be equal to pull up voltage.
④ When VIN rises above the VSS level (excepting levels lower than minimum operating voltage), VOUT will be equal to
VSS until VIN reaches the VDR level.
⑤ Although VIN will rise to a level higher than VDR, VOUT maintains ground voltage level via the delay circuit.
⑥ Following transient delay time, VIN will be output at VOUT. Note that high impedance exists with the N-channel open
drain configuration and that voltage will be dependent on pull up.
Notes:
1. The difference between VDR and VDF represents the hysteresis range.
2. Propagation delay time (tDLY) represents the time it takes for VIN to appear at VOUT once the said voltage has
exceeded the VDR level.
●Timing Chart
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