T436432B Datasheet, PDF (48/72 Pages) Taiwan Memory Technology – 2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM

tm TE
CH
T436432B
Figure 14.2. Interleaving Column Read Cycle (Burst Length=4, CAS# Latency=2)
CLK
CKE
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 ^T22
tCK2
CS#
RAS#
CAS#
WE#
BS0,1
A10
RAx
RAx
A0~A9
DQM
RAx
CAy
RAx
tRCD
tAC2
CBw
CBx
CBy
CAy
CBz
DQ ^Hi-Z
Ax0 Ax1 Ax2 Ax3 _{Bw0 Bw1 Bx0 Bx1} By0 _{By1 Ay0} Ay1 _Bz0 Bz1 ^{Bz2 Bz3}
Activate
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank B
Read
Read
Command Command
Bank B Bank B
Read
Command
Bank B
Read
Command
Bank A
Read
Command
Bank B
Precharge
Command
Bank A
Precharge
Command
Bank B
TM Technology Inc. reserves the right
P. 48
to change products or specifications without notice.
Publication Date: FEB. 2007
Revision: A