T436432B Datasheet, PDF(29/72 Page) Taiwan Memory Technology – 2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM

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T436432B Datasheet, PDF (29/72 Pages) Taiwan Memory Technology – 2M x 32 SDRAM 512K x 32bit x 4Banks Synchronous DRAM

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tm TE

T436432B

Figure 7.2. Clock Suspension During Burst Write (Using CKE)

(Burst Length=4, CAS# Latency=2)

CL K

CKE

CS#

RAS#

CAS#

WE #

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

tCK2

BA0,1

A10

RAx

A0-A9

RAx

CAx

DQM

DQHi-Z

DAx0

DAx1

DAx2

DAx3

Activate

Clock Suspend Clock Suspend

Command

1 Cycle

2 Cycles

Bank A

Write

Command

Bank A

Note: CKE to CLK disable/enable = 1 clock

Clock Suspend

3 Cycles

TM Technology Inc. reserves the right

P. 29

to change products or specifications without notice.

Publication Date: FEB. 2007

Revision: A

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