LM3S9D90 Datasheet, PDF (995/1310 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Stellaris^® LM3S9D90 Microcontroller
Register 27: Ethernet PHY Management Register 29 – Interrupt Status (MR29),
address 0x1D
This register contains information about the source of PHY layer interrupts. Reading this register
clears any bits that are set. The PHYINT bit is set in the MACRIS/MACIACK register whenever any
of the bits in this register are set.
Ethernet PHY Management Register 29 – Interrupt Status (MR29)
Base 0x4004.8000
Address 0x1D
Type RO, reset 0x0000
15
14
13
12
11
10
9
8
7
6
5
reserved
EONIS ANCOMPIS RFLTIS
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
4
3
2
LDIS LPACKIS PDFIS
RO
RO
RO
0
0
0
1
PRXIS
RO
0
0
reserved
RO
0
Bit/Field
15:8
7
6
5
4
Name
reserved
EONIS
ANCOMPIS
RFLTIS
LDIS
Type
RO
RO
RO
RO
RO
Reset
0x00
0
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
ENERGYON Interrupt
Value Description
1 An interrupt has been generated due to the ENON bit being set
in the MR17 register.
0 No interrupt.
This bit is cleared by reading the value.
Auto-Negotiation Complete Interrupt
Value Description
1 An interrupt has been generated due to the completion of auto
negotiation.
0 No interrupt.
This bit is cleared by reading the value.
Remote Fault Interrupt
Value Description
1 An interrupt has been generated due to the detection of a
Remote Fault.
0 No interrupt.
This bit is cleared by reading the value.
Link Down Interrupt
Value Description
1 An interrupt has been generated because the LINK bit in MR1
is clear.
0 No interrupt.
This bit is cleared by reading the value.
January 22, 2012
995
Texas Instruments-Production Data