LM3S9D90 Datasheet, PDF (13/1310 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Stellaris^® LM3S9D90 Microcontroller
Figure 15-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 780
Figure 15-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 781
Figure 15-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 781
Figure 15-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 782
Figure 15-10. MICROWIRE Frame Format (Single Frame) ........................................................ 783
Figure 15-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 784
Figure 15-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 784
Figure 16-1. I²C Block Diagram ............................................................................................. 816
Figure 16-2. I²C Bus Configuration ........................................................................................ 817
Figure 16-3. START and STOP Conditions ............................................................................. 818
Figure 16-4. Complete Data Transfer with a 7-Bit Address ....................................................... 818
Figure 16-5. R/S Bit in First Byte ............................................................................................ 819
Figure 16-6. Data Validity During Bit Transfer on the I²C Bus ................................................... 819
Figure 16-7. Master Single TRANSMIT .................................................................................. 823
Figure 16-8. Master Single RECEIVE ..................................................................................... 824
Figure 16-9. Master TRANSMIT with Repeated START ........................................................... 825
Figure 16-10. Master RECEIVE with Repeated START ............................................................. 826
Figure 16-11. Master RECEIVE with Repeated START after TRANSMIT with Repeated
START .............................................................................................................. 827
Figure 16-12. Master TRANSMIT with Repeated START after RECEIVE with Repeated
START .............................................................................................................. 828
Figure 16-13. Slave Command Sequence ................................................................................ 829
Figure 17-1. I²S Block Diagram ............................................................................................. 854
Figure 17-2. I²S Data Transfer ............................................................................................... 857
Figure 17-3. Left-Justified Data Transfer ................................................................................ 857
Figure 17-4. Right-Justified Data Transfer .............................................................................. 857
Figure 18-1. CAN Controller Block Diagram ............................................................................ 891
Figure 18-2. CAN Data/Remote Frame .................................................................................. 893
Figure 18-3. Message Objects in a FIFO Buffer ...................................................................... 901
Figure 18-4. CAN Bit Time .................................................................................................... 905
Figure 19-1. Ethernet Controller ............................................................................................. 942
Figure 19-2. Ethernet Controller Block Diagram ...................................................................... 942
Figure 19-3. Ethernet Frame ................................................................................................. 944
Figure 19-4. Interface to an Ethernet Jack .............................................................................. 951
Figure 20-1. USB Module Block Diagram ............................................................................. 1001
Figure 21-1. Analog Comparator Module Block Diagram ....................................................... 1140
Figure 21-2. Structure of Comparator Unit ............................................................................ 1142
Figure 21-3. Comparator Internal Reference Structure .......................................................... 1142
Figure 22-1. 100-Pin LQFP Package Pin Diagram ................................................................ 1153
Figure 22-2. 108-Ball BGA Package Pin Diagram (Top View) ................................................. 1154
Figure 25-1. Load Conditions ............................................................................................... 1223
Figure 25-2. JTAG Test Clock Input Timing ........................................................................... 1224
Figure 25-3. JTAG Test Access Port (TAP) Timing ................................................................ 1224
Figure 25-4. Power-On Reset Timing ................................................................................... 1225
Figure 25-5. Brown-Out Reset Timing .................................................................................. 1225
Figure 25-6. Power-On Reset and Voltage Parameters ......................................................... 1226
Figure 25-7. External Reset Timing (RST) ............................................................................ 1226
Figure 25-8. Software Reset Timing ..................................................................................... 1226
January 22, 2012
13
Texas Instruments-Production Data