SM320C6711-EP Datasheet, PDF (98/128 Pages) Texas Instruments – FLOATING-POINT DIGTAL SIGNAL PROCESSORS

SM320C6711ĆEP, SM320C6711BĆEP, SM320C6711CĆEP, SM320C6711DĆEP
FLOATINGĆPOINT DIGITAL SIGNAL PROCESSORS
SGUS054 − AUGUST 2004
HOST-PORT INTERFACE TIMING (CONTINUED)
timing requirements for host-port interface cycles^†‡ (see Figure 46 through Figure 49)
[C6711C/C6711D]
NO.
11CGDPA-167
11C−200
11DGDPA-167
11D−200
11D−250
UNIT
1 tsu(SELV-HSTBL) Setup time, select signals¶ valid before HSTROBE low
2 th(HSTBL-SELV) Hold time, select signals¶ valid after HSTROBE low
3 tw(HSTBL)
Pulse duration, HSTROBE low (host read access)
Pulse duration, HSTROBE low (host write access)
MIN
5
4
10P + 5.8
4P
MAX
MIN MAX
5
ns
4
ns
4P
ns
4P
ns
Pulse duration, HSTROBE high between consecutive
4 tw(HSTBH)
accesses
4P
10 tsu(SELV-HASL) Setup time, select signals¶ valid before HAS low
5
11 th(HASL-SELV) Hold time, select signals¶ valid after HAS low
3
12 tsu(HDV-HSTBH) Setup time, host data valid before HSTROBE high
5
13 th(HSTBH-HDV) Hold time, host data valid after HSTROBE high
3
Hold time, HSTROBE low after HRDY low. HSTROBE should
14 th(HRDYL-HSTBL) not be inactivated until HRDY is active (low); otherwise, HPI
2
writes will not complete properly.
4P
ns
5
ns
3
ns
5
ns
3
ns
2
ns
18 tsu(HASL-HSTBL) Setup time, HAS low before HSTROBE low
2
2
ns
19 th(HSTBL-HASL) Hold time, HAS low after HSTROBE low
2
2
ns
† _{HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.}
‡ _{P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.}
§ _{Make sure the external host meets the timing specifications of the C6711 device. Delays or buffers may be needed to compensate for any timing}
differences. IBIS analysis should be used to correctly model the system interface.
¶ _{Select signals include: HCNTL[1:0], HR/W, and HHWIL.}
98
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